From 9c23c347251986dc9757afe20c00a21c45324a6d Mon Sep 17 00:00:00 2001
From: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Date: Mon, 5 Aug 2019 12:58:18 -0700
Subject: [PATCH] pinctrl: Add api to enable/disable wakeup capability for a
 gpio

Add api to write to mpm wakeup registers to configure a gpio
as wakeup capable.

Change-Id: Ia11a22160394e76969200691cfaf8fb1505bf5c1
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c   | 30 ++++++++++++++++++++++++++++
 drivers/pinctrl/qcom/pinctrl-msm.h   |  5 +++++
 include/linux/pinctrl/qcom-pinctrl.h |  2 ++
 3 files changed, 37 insertions(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 46b1bd28cb70..eb85d9803431 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -1168,6 +1168,36 @@ int msm_qup_read(unsigned int mode)
 	return -ENOENT;
 }
 
+/*
+ * msm_gpio_mpm_wake_set - API to make interrupt wakeup capable
+ * @dev:        Device corrsponding to pinctrl
+ * @gpio:       Gpio number to make interrupt wakeup capable
+ * @enable:     Enable/Disable wakeup capability
+ */
+int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable)
+{
+	const struct msm_pingroup *g;
+	unsigned long flags;
+	u32 val;
+
+	g = &msm_pinctrl_data->soc->groups[gpio];
+	if (g->wake_bit == -1)
+		return -ENOENT;
+
+	raw_spin_lock_irqsave(&msm_pinctrl_data->lock, flags);
+	val = readl_relaxed(msm_pinctrl_data->regs[g->tile] + g->wake_reg);
+	if (enable)
+		val |= BIT(g->wake_bit);
+	else
+		val &= ~BIT(g->wake_bit);
+
+	writel_relaxed(val, msm_pinctrl_data->regs[g->tile] + g->wake_reg);
+	raw_spin_unlock_irqrestore(&msm_pinctrl_data->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(msm_gpio_mpm_wake_set);
+
 int msm_pinctrl_probe(struct platform_device *pdev,
 		      const struct msm_pinctrl_soc_data *soc_data)
 {
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 3eaabe3f23f0..06dbb6d0cf0c 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -55,6 +55,8 @@ struct msm_function {
  * @intr_detection_width: Number of bits used for specifying interrupt type,
  *                        Should be 2 for SoCs that can detect both edges in hardware,
  *                        otherwise 1.
+ * @wake_reg:             Offset of the WAKEUP_INT_EN register from base tile
+ * @wake_bit:             Bit number for the corresponding gpio
  */
 struct msm_pingroup {
 	const char *name;
@@ -93,6 +95,9 @@ struct msm_pingroup {
 	unsigned intr_polarity_bit:5;
 	unsigned intr_detection_bit:5;
 	unsigned intr_detection_width:5;
+
+	u32 wake_reg;
+	unsigned int wake_bit;
 };
 
 /*
diff --git a/include/linux/pinctrl/qcom-pinctrl.h b/include/linux/pinctrl/qcom-pinctrl.h
index 1ea9a870514a..f14d63ca8556 100644
--- a/include/linux/pinctrl/qcom-pinctrl.h
+++ b/include/linux/pinctrl/qcom-pinctrl.h
@@ -10,5 +10,7 @@
 int msm_qup_write(u32 mode, u32 val);
 int msm_qup_read(u32 mode);
 
+/* API to write to mpm_wakeup registers */
+int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable);
 
 #endif /* __LINUX_PINCTRL_MSM_H__ */