From e46fe1c97c4ea24a16630ba2a8efe88ead8cf024 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Wed, 28 Oct 2020 15:00:21 +0530 Subject: [PATCH 1/3] ARM: dts: msm: Add USB Phy Support on Yupik Add USB Phy support for primary and secondary controller on Yupik. Change-Id: I04229c74d8d78a63f8a560007071f1007df61327 --- qcom/yupik-usb.dtsi | 255 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 252 insertions(+), 3 deletions(-) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index c33d2f3e6f02..4117781f37b6 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -1,4 +1,5 @@ #include +#include &soc { /* Primary USB port related controller */ @@ -31,7 +32,7 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; - qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = @@ -43,11 +44,20 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; usb-role-switch; + extcon = <&eud>; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>; + + qcom,usb-charger = <&battery_charger>; dwc3@a600000 { compatible = "snps,dwc3"; reg = <0xa600000 0xe000>; interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; @@ -69,6 +79,218 @@ }; }; + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x114>, + <0x088e2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L10C>; + vdda18-supply = <&L1C>; + vdda33-supply = <&L2B>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; /* override_x1 */ + }; + + /* Primary USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L1B>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L6B>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + + }; + usb1: hsusb@8c00000 { status = "disabled"; compatible = "qcom,dwc-usb3-msm"; @@ -98,8 +320,7 @@ resets = <&gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset"; - qcom,core-clk-rate = <120000000>; - qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate = <60000000>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ @@ -114,6 +335,7 @@ compatible = "snps,dwc3"; reg = <0x8c00000 0xe000>; interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_nop_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; @@ -130,7 +352,34 @@ }; + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e4000 { + status = "disabled"; + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e4000 0x114>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&L10C>; + vdda18-supply = <&L1C>; + vdda33-supply = <&L2B>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + }; + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x180f 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; }; From 34bda24dfcc30740e53b137e2f2197f2a90b960f Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Wed, 16 Dec 2020 18:40:37 +0530 Subject: [PATCH 2/3] ARM: dts: msm: Add SMMU nodes for Yupik Adding SMMU nodes for Yupik for both primary and secondary controller. Change-Id: I2fa53e633403b159845b6329a9d327d9005d3df0 --- qcom/yupik-usb.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 4117781f37b6..24d67f57fe97 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -8,9 +8,14 @@ reg = <0xa600000 0x100000>; reg-names = "core_base"; + iommus = <&apps_smmu 0xe0 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; #address-cells = <1>; #size-cells = <1>; ranges; + dma-ranges; interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, @@ -297,6 +302,9 @@ reg = <0x8c00000 0x100000>; reg-names = "core_base"; + iommus = <&apps_smmu 0xa0 0x0>; + qcom,iommu-dma = "bypass"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; #address-cells = <1>; #size-cells = <1>; ranges; From f4fb1be921224f358b7ad26b4b44dff2f5a3c901 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Wed, 16 Dec 2020 19:02:09 +0530 Subject: [PATCH 3/3] ARM: dts: msm: Add pm-qos-latency for Yupik Add pm-qos-latency which ensures that cpu is used to its full capability, therefore increasing USB throughput for Yupik. Adding the parameter for both controllers. Change-Id: Ifb01d6d156ef17abe6dcbda33ab78978e2b17757 --- qcom/yupik-usb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi index 24d67f57fe97..137e2b4bcd91 100644 --- a/qcom/yupik-usb.dtsi +++ b/qcom/yupik-usb.dtsi @@ -40,6 +40,7 @@ qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; + qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ @@ -330,6 +331,7 @@ qcom,core-clk-rate = <60000000>; qcom,num-gsi-evt-buffs = <0x3>; + qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */