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pinctrl: qcom: Expose ufs_reset as gpio on Lahaina
The ufs_reset pin is expected to be wired to the reset pin of the primary UFS memory but is pretty much just a general purpose output pin. Reorder the pins and expose it as gpio 203, so that the UFS driver can toggle it. Change-Id: I412e8a2aac51fd9434cbe63d4521ede31254d7fe Signed-off-by: Can Guo <cang@codeaurora.org>
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1 changed files with 9 additions and 9 deletions
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@ -536,10 +536,10 @@ DECLARE_MSM_GPIO_PINS(200);
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DECLARE_MSM_GPIO_PINS(201);
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DECLARE_MSM_GPIO_PINS(202);
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static const unsigned int sdc2_clk_pins[] = { 203 };
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static const unsigned int sdc2_cmd_pins[] = { 204 };
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static const unsigned int sdc2_data_pins[] = { 205 };
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static const unsigned int ufs_reset_pins[] = { 206 };
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static const unsigned int ufs_reset_pins[] = { 203 };
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static const unsigned int sdc2_clk_pins[] = { 204 };
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static const unsigned int sdc2_cmd_pins[] = { 205 };
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static const unsigned int sdc2_data_pins[] = { 206 };
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enum lahaina_functions {
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msm_mux_gpio,
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@ -1843,10 +1843,10 @@ static const struct msm_pingroup lahaina_groups[] = {
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[200] = PINGROUP(200, qdss_gpio15, NA, NA, NA, NA, NA, NA, NA, NA),
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[201] = PINGROUP(201, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[202] = PINGROUP(202, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[203] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1cf000, 14, 6),
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[204] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1cf000, 11, 3),
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[205] = SDC_QDSD_PINGROUP(sdc2_data, 0x1cf000, 9, 0),
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[206] = UFS_RESET(ufs_reset, 0x1d8000),
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[203] = UFS_RESET(ufs_reset, 0x1d8000),
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[204] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1cf000, 14, 6),
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[205] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1cf000, 11, 3),
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[206] = SDC_QDSD_PINGROUP(sdc2_data, 0x1cf000, 9, 0),
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};
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static const int lahaina_reserved_gpios[] = {
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@ -1886,7 +1886,7 @@ static const struct msm_pinctrl_soc_data lahaina_pinctrl = {
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.groups = lahaina_groups,
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.ngroups = ARRAY_SIZE(lahaina_groups),
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.reserved_gpios = lahaina_reserved_gpios,
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.ngpios = 203,
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.ngpios = 204,
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.qup_regs = lahaina_qup_regs,
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.nqup_regs = ARRAY_SIZE(lahaina_qup_regs),
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.wakeirq_map = lahaina_pdc_map,
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