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Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
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9c861f3328
8 changed files with 17 additions and 7 deletions
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#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
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#define _DT_BINDINGS_CLK_SUN50I_A64_H_
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#define CLK_PLL_PERIPH0 11
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#define CLK_BUS_MIPI_DSI 28
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#define CLK_BUS_CE 29
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#define CLK_BUS_DMA 30
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#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
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#define _DT_BINDINGS_CLK_SUN8I_H3_H_
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#define CLK_PLL_PERIPH0 9
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#define CLK_CPUX 14
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#define CLK_BUS_CE 20
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