From 47da81107ad2927c4c2a11551d5ee065fee5ebcc Mon Sep 17 00:00:00 2001 From: Raghu Ananya Arabolu Date: Thu, 19 Dec 2019 17:22:15 -0800 Subject: [PATCH] msm: kgsl: Calculate the offset of context bank 0 The context bank 0 offset and size of each context bank register space was hardcoded. The context bank 0 offset changed in A660. We now compute these values from GPU_GFX_SMMU_IDR1 register instead of using hardcoded values. Change-Id: If9125dfe823f92e9c61ff1635ae07a13ec6f000b Signed-off-by: Raghu Ananya Arabolu --- drivers/gpu/msm/kgsl_iommu.c | 21 +++++++++++++++++++-- drivers/gpu/msm/kgsl_iommu.h | 7 ------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c index d615ebcae95d..6391409eda8d 100644 --- a/drivers/gpu/msm/kgsl_iommu.c +++ b/drivers/gpu/msm/kgsl_iommu.c @@ -3,6 +3,7 @@ * Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -35,6 +36,10 @@ #define IOMMU_USE_UPSTREAM_HINT 0 #endif +#define KGSL_IOMMU_IDR1_OFFSET 0x24 +#define IDR1_NUMPAGENDXB GENMASK(30, 28) +#define IDR1_PAGESIZE BIT(31) + static struct kgsl_mmu_pt_ops iommu_pt_ops; const unsigned int kgsl_iommu_reg_list[KGSL_IOMMU_REG_MAX] = { @@ -931,7 +936,11 @@ static int _init_global_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) struct kgsl_device *device = KGSL_MMU_DEVICE(mmu); int ret = 0; struct kgsl_iommu_pt *iommu_pt = NULL; + unsigned int mmu_idr1; + unsigned int mmu_pagesize; + unsigned int mmu_npages; unsigned int cb_num; + unsigned int cb0_offset; struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu); struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER]; @@ -977,8 +986,16 @@ static int _init_global_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) } ctx->cb_num = cb_num; - ctx->regbase = iommu->regbase + KGSL_IOMMU_CB0_OFFSET - + (cb_num << KGSL_IOMMU_CB_SHIFT); + mmu_idr1 = readl_relaxed(iommu->regbase + KGSL_IOMMU_IDR1_OFFSET); + mmu_pagesize = FIELD_GET(IDR1_PAGESIZE, mmu_idr1) ? SZ_64K : SZ_4K; + + /* + * The number of pages in the global address space or translation + * bank address space is 2^(NUMPAGENDXB + 1). + */ + mmu_npages = 1 << (FIELD_GET(IDR1_NUMPAGENDXB, mmu_idr1) + 1); + cb0_offset = mmu_pagesize * mmu_npages; + ctx->regbase = iommu->regbase + cb0_offset + (cb_num * mmu_pagesize); ret = iommu_domain_get_attr(iommu_pt->domain, DOMAIN_ATTR_TTBR0, &iommu_pt->ttbr0); diff --git a/drivers/gpu/msm/kgsl_iommu.h b/drivers/gpu/msm/kgsl_iommu.h index 8b4f7e3952b7..dba254397a66 100644 --- a/drivers/gpu/msm/kgsl_iommu.h +++ b/drivers/gpu/msm/kgsl_iommu.h @@ -157,13 +157,6 @@ struct kgsl_iommu_pt { uint64_t compat_va_end; }; -/* - * offset of context bank 0 from the start of the SMMU register space. - */ -#define KGSL_IOMMU_CB0_OFFSET 0x8000 -/* size of each context bank's register space */ -#define KGSL_IOMMU_CB_SHIFT 12 - /* Macros to read/write IOMMU registers */ extern const unsigned int kgsl_iommu_reg_list[KGSL_IOMMU_REG_MAX];