mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc updates from Benjamin Herrenschmidt:
"So from the depth of frozen Minnesota, here's the powerpc pull request
for 3.9. It has a few interesting highlights, in addition to the
usual bunch of bug fixes, minor updates, embedded device tree updates
and new boards:
- Hand tuned asm implementation of SHA1 (by Paulus & Michael
Ellerman)
- Support for Doorbell interrupts on Power8 (kind of fast
thread-thread IPIs) by Ian Munsie
- Long overdue cleanup of the way we handle relocation of our open
firmware trampoline (prom_init.c) on 64-bit by Anton Blanchard
- Support for saving/restoring & context switching the PPR (Processor
Priority Register) on server processors that support it. This
allows the kernel to preserve thread priorities established by
userspace. By Haren Myneni.
- DAWR (new watchpoint facility) support on Power8 by Michael Neuling
- Ability to change the DSCR (Data Stream Control Register) which
controls cache prefetching on a running process via ptrace by
Alexey Kardashevskiy
- Support for context switching the TAR register on Power8 (new
branch target register meant to be used by some new specific
userspace perf event interrupt facility which is yet to be enabled)
by Ian Munsie.
- Improve preservation of the CFAR register (which captures the
origin of a branch) on various exception conditions by Paulus.
- Move the Bestcomm DMA driver from arch powerpc to drivers/dma where
it belongs by Philippe De Muyter
- Support for Transactional Memory on Power8 by Michael Neuling
(based on original work by Matt Evans). For those curious about
the feature, the patch contains a pretty good description."
(See commit db8ff90702: "powerpc: Documentation for transactional
memory on powerpc" for the mentioned description added to the file
Documentation/powerpc/transactional_memory.txt)
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (140 commits)
powerpc/kexec: Disable hard IRQ before kexec
powerpc/85xx: l2sram - Add compatible string for BSC9131 platform
powerpc/85xx: bsc9131 - Correct typo in SDHC device node
powerpc/e500/qemu-e500: enable coreint
powerpc/mpic: allow coreint to be determined by MPIC version
powerpc/fsl_pci: Store the pci ctlr device ptr in the pci ctlr struct
powerpc/85xx: Board support for ppa8548
powerpc/fsl: remove extraneous DIU platform functions
arch/powerpc/platforms/85xx/p1022_ds.c: adjust duplicate test
powerpc: Documentation for transactional memory on powerpc
powerpc: Add transactional memory to pseries and ppc64 defconfigs
powerpc: Add config option for transactional memory
powerpc: Add transactional memory to POWER8 cpu features
powerpc: Add new transactional memory state to the signal context
powerpc: Hook in new transactional memory code
powerpc: Routines for FP/VSX/VMX unavailable during a transaction
powerpc: Add transactional memory unavaliable execption handler
powerpc: Add reclaim and recheckpoint functions for context switching transactional memory processes
powerpc: Add FP/VSX and VMX register load functions for transactional memory
powerpc: Add helper functions for transactional memory context switching
...
This commit is contained in:
Linus Torvalds
commit
9d3cae26ac
201 changed files with 7075 additions and 2581 deletions
|
|
@ -54,8 +54,13 @@ PROPERTIES
|
|||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must include "fsl,sec-v4.0". Also includes SEC
|
||||
ERA versions (optional) with which the device is compatible.
|
||||
Definition: Must include "fsl,sec-v4.0"
|
||||
|
||||
- fsl,sec-era
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: A standard property. Define the 'ERA' of the SEC
|
||||
device.
|
||||
|
||||
- #address-cells
|
||||
Usage: required
|
||||
|
|
@ -107,7 +112,8 @@ PROPERTIES
|
|||
|
||||
EXAMPLE
|
||||
crypto@300000 {
|
||||
compatible = "fsl,sec-v4.0", "fsl,sec-era-v2.0";
|
||||
compatible = "fsl,sec-v4.0";
|
||||
fsl,sec-era = <0x2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
|
|
|
|||
|
|
@ -17,9 +17,20 @@ Recommended properties:
|
|||
contains a functioning "reset control register" (i.e. the board
|
||||
is wired to reset upon setting the HRESET_REQ bit in this register).
|
||||
|
||||
Example:
|
||||
- fsl,liodn-bits : Indicates the number of defined bits in the LIODN
|
||||
registers, for those SOCs that have a PAMU device.
|
||||
|
||||
Examples:
|
||||
global-utilities@e0000 { /* global utilities block */
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <e0000 1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
|
|
|||
140
Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
Normal file
140
Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding
|
||||
|
||||
DESCRIPTION
|
||||
|
||||
The PAMU is an I/O MMU that provides device-to-memory access control and
|
||||
address translation capabilities.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : <string>
|
||||
First entry is a version-specific string, such as
|
||||
"fsl,pamu-v1.0". The second is "fsl,pamu".
|
||||
- ranges : <prop-encoded-array>
|
||||
A standard property. Utilized to describe the memory mapped
|
||||
I/O space utilized by the controller. The size should
|
||||
be set to the total size of the register space of all
|
||||
physically present PAMU controllers. For example, for
|
||||
PAMU v1.0, on an SOC that has five PAMU devices, the size
|
||||
is 0x5000.
|
||||
- interrupts : <prop-encoded-array>
|
||||
Interrupt mappings. The first tuple is the normal PAMU
|
||||
interrupt, used for reporting access violations. The second
|
||||
is for PAMU hardware errors, such as PAMU operation errors
|
||||
and ECC errors.
|
||||
- #address-cells: <u32>
|
||||
A standard property.
|
||||
- #size-cells : <u32>
|
||||
A standard property.
|
||||
|
||||
Optional properties:
|
||||
- reg : <prop-encoded-array>
|
||||
A standard property. It represents the CCSR registers of
|
||||
all child PAMUs combined. Include it to provide support
|
||||
for legacy drivers.
|
||||
- interrupt-parent : <phandle>
|
||||
Phandle to interrupt controller
|
||||
|
||||
Child nodes:
|
||||
|
||||
Each child node represents one PAMU controller. Each SOC device that is
|
||||
connected to a specific PAMU device should have a "fsl,pamu-phandle" property
|
||||
that links to the corresponding specific child PAMU controller.
|
||||
|
||||
- reg : <prop-encoded-array>
|
||||
A standard property. Specifies the physical address and
|
||||
length (relative to the parent 'ranges' property) of this
|
||||
PAMU controller's configuration registers. The size should
|
||||
be set to the size of this PAMU controllers's register space.
|
||||
For PAMU v1.0, this size is 0x1000.
|
||||
- fsl,primary-cache-geometry
|
||||
: <prop-encoded-array>
|
||||
Two cells that specify the geometry of the primary PAMU
|
||||
cache. The first is the number of cache lines, and the
|
||||
second is the number of "ways". For direct-mapped caches,
|
||||
specify a value of 1.
|
||||
- fsl,secondary-cache-geometry
|
||||
: <prop-encoded-array>
|
||||
Two cells that specify the geometry of the secondary PAMU
|
||||
cache. The first is the number of cache lines, and the
|
||||
second is the number of "ways". For direct-mapped caches,
|
||||
specify a value of 1.
|
||||
|
||||
Device nodes:
|
||||
|
||||
Devices that have LIODNs need to specify links to the parent PAMU controller
|
||||
(the actual PAMU controller that this device is connected to) and a pointer to
|
||||
the LIODN register, if applicable.
|
||||
|
||||
- fsl,iommu-parent
|
||||
: <phandle>
|
||||
Phandle to the single, specific PAMU controller node to which
|
||||
this device is connect. The PAMU topology is represented in
|
||||
the device tree to assist code that dynamically determines the
|
||||
best LIODN values to minimize PAMU cache thrashing.
|
||||
|
||||
- fsl,liodn-reg : <prop-encoded-array>
|
||||
Two cells that specify the location of the LIODN register
|
||||
for this device. Required for devices that have a single
|
||||
LIODN. The first cell is a phandle to a node that contains
|
||||
the registers where the LIODN is to be set. The second is
|
||||
the offset from the first "reg" resource of the node where
|
||||
the specific LIODN register is located.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x5000>;
|
||||
ranges = <0 0x20000 0x5000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu1: pamu@1000 {
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu2: pamu@2000 {
|
||||
reg = <0x2000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu3: pamu@3000 {
|
||||
reg = <0x3000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu4: pamu@4000 {
|
||||
reg = <0x4000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
Loading…
Reference in a new issue