From 9d50a8c24efbfd0731f064a35c1d601065adcba0 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 23 Feb 2021 18:17:49 +0530 Subject: [PATCH] ARM: dts: msm: Add qcom,no-accumulative-counter property for cpufreq Accumulative cycle counters are not supported, cycle counter needs to be read from the core-0 of the frequency domain. Add property to indicate the same. Change-Id: I503c4470824d29ee95a3c39a172ec716be77c61b --- qcom/sdmshrike.dtsi | 1 + qcom/sm6150.dtsi | 1 + qcom/sm8150.dtsi | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6e7b1c5ec1a5..eb071d23cb9a 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1331,6 +1331,7 @@ reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; + qcom,no-accumulative-counter; #freq-domain-cells = <2>; }; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b40eb0bb1ce9..c2d68da84898 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1360,6 +1360,7 @@ reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; + qcom,no-accumulative-counter; #freq-domain-cells = <2>; }; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 2b998b1e9732..fd86394b8357 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1068,7 +1068,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - + qcom,no-accumulative-counter; #freq-domain-cells = <2>; };