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disp: msm: sde: program read pointer after configuring vsync_counter_en

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Program the read pointer after configuring the tearcheck registers.
The read pointer register should be configured after VSYNC_COUNTER_EN
is set as per hw programming sequence.

Change-Id: I2fa1429798fab51d08091e74a33f1b1c4382eafe
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
(cherry picked from commit fce2fc595f1a9881255faa651e8d1b9e43cbf906)
This commit is contained in:
Akash Gajjar 2022-12-22 19:02:46 +05:30 • committed by Raghavendra Ambadas
commit 9d53b47d4e
1 changed files with 4 additions and 2 deletions
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6
msm/sde/sde_hw_intf.c
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@ -565,8 +565,6 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
* less than 2^16 vsync clk cycles.
*/
spin_lock(&tearcheck_spinlock);
SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,
(te->start_pos + te->sync_threshold_start + 1));
SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
wmb(); /* disable vsync counter before updating single buffer registers */
SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
@ -579,6 +577,10 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
te->sync_threshold_start));
cfg |= BIT(19); /* VSYNC_COUNTER_EN */
SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
wmb(); /* ensure vsync_counter_en is written */
SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,
(te->start_pos + te->sync_threshold_start + 1));
spin_unlock(&tearcheck_spinlock);
return 0;