From e6e557be9f2e43c875436e866b06a7ac97246d06 Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Wed, 5 Feb 2020 12:55:52 -0800 Subject: [PATCH] ARM: dts: msm: Update Lahaina USB3 QMP UNI PHY init settings Update USB3 UNI PHY initialization sequence to the latest HW recommended values to improve SuperSpeed/SuperSpeedPlus performance. Change-Id: Id3c39ad6a369df83feddd83aacd7743db5b3faa0 --- qcom/lahaina-usb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index 5ab5b937f85c..fe21d50ad716 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -480,7 +480,7 @@ USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xB8 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xFF 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xBF 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xB7 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0 USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x7F 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xB4 0 @@ -508,6 +508,7 @@ USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0 USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0 USB3_UNI_QSERDES_RX_GM_CAL 0x1F 0 + USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0 USB3_UNI_QSERDES_TX_LANE_MODE_1 0xD5 0 USB3_UNI_QSERDES_TX_LANE_MODE_2 0x80 0 USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0