From b77c2fed79eecc2e80c9563da91008c18b593b52 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 29 Dec 2020 13:07:17 +0530 Subject: [PATCH] ARM: dts: msm: Update DISPCC and debugcc clock nodes for YUPIK Update the display clock controller node to real from dummmy and add debug clock controller node for YUPIK. Change-Id: I2211792d6c26f7f234cc507129438e52106971f6 --- qcom/yupik-rumi.dtsi | 9 +++++++++ qcom/yupik.dtsi | 33 +++++++++++++++++++++++++++++++-- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 83894d7154ca..5cc8fca9f758 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -191,3 +191,12 @@ clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>; status = "disabled"; }; + +&dispcc { + clocks = <&bi_tcxo>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_AHB_CLK>; +}; + +&debugcc { + clocks = <&bi_tcxo>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 923e3eba9e03..22c0fff9524c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -951,8 +951,13 @@ }; dispcc: clock-controller@af00000 { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + compatible = "qcom,yupik-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", "gcc_disp_gpll0_clk","cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -983,6 +988,30 @@ #reset-cells = <1>; }; + apsscc: syscon@182a0000 { + compatible = "syscon"; + reg = <0x182a0000 0x1c>; + }; + + mccc: syscon@90ba000 { + compatible = "syscon"; + reg = <0x90ba000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,yupik-debugcc"; + qcom,gcc = <&gcc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,gpucc = <&gpucc>; + qcom,videocc = <&videocc>; + qcom,apsscc = <&apsscc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + cpufreq_hw: qcom,cpufreq-hw { compatible = "qcom,cpufreq-hw-epss"; reg = <0x18591000 0x1000>, <0x18592000 0x1000>,