diff --git a/bindings/spmi/qcom,spmi-glink-debug.txt b/bindings/spmi/qcom,spmi-glink-debug.txt
new file mode 100644
index 000000000000..454ea8b66172
--- /dev/null
+++ b/bindings/spmi/qcom,spmi-glink-debug.txt
@@ -0,0 +1,52 @@
+Qualcomm Technologies, Inc. Glink SPMI Debug Controller
+
+The Qualcomm Technologies, Inc. Glink SPMI debug controller device provides an
+interface to read and write PMIC registers over PMIC Glink using a remote
+subsytem (e.g. DSP).  This allows for debugging PMIC peripherals that would
+typically only be accessible to the charger and fuel gauging firmware running
+on the remote subsystem.
+
+Refer to Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.txt for
+information on "qcom,pmic_glink_log" device which is used in the example below.
+
+See spmi.txt for the generic SPMI controller binding requirements for grandchild
+nodes.
+
+Required device node structure:
+
+The Glink SPMI debug controller node must contain at least one child node.  Each
+child node corresponds to an SPMI bus accessible from the remote subsystem.
+
+Top Level Node Supported Properties:
+
+- compatible:
+	Usage:      required
+	Value type: <stringlist>
+	Definition: Must be "qcom,spmi-glink-debug".
+
+Child Node Supported Properties:
+
+- reg
+	Usage:      required
+	Value type: <u32>
+	Definition: Bus ID of this SPMI bus.
+
+Example:
+
+&soc {
+	qcom,pmic_glink_log {
+		qcom,spmi_glink_debug {
+			compatible = "qcom,spmi-glink-debug";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			spmi@0 {
+				reg = <0>;
+			};
+
+			spmi@1 {
+				reg = <1>;
+			};
+		};
+	};
+};
diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi
index 481c5ca2bd64..8fc347889536 100644
--- a/qcom/lahaina-cdp.dtsi
+++ b/qcom/lahaina-cdp.dtsi
@@ -9,6 +9,10 @@
 	status = "ok";
 };
 
+&spmi_glink_debug {
+	status = "ok";
+};
+
 &soc {
 	gpio_keys {
 		compatible = "gpio-keys";
diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi
index 6a15a7b6df6e..0c4ec8d84d93 100644
--- a/qcom/lahaina-mtp.dtsi
+++ b/qcom/lahaina-mtp.dtsi
@@ -9,6 +9,10 @@
 	status = "ok";
 };
 
+&spmi_glink_debug {
+	status = "ok";
+};
+
 &soc {
 	gpio_keys {
 		compatible = "gpio-keys";
diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi
index 0f783793ab08..3a8669672b47 100644
--- a/qcom/lahaina-qrd-common.dtsi
+++ b/qcom/lahaina-qrd-common.dtsi
@@ -7,6 +7,14 @@
 	status = "ok";
 };
 
+&spmi_glink_debug {
+	status = "ok";
+};
+
+&smb1398_debug {
+	status = "ok";
+};
+
 &soc {
 	gpio_keys {
 		compatible = "gpio-keys";
diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index 1505a4d0e66a..3baaa6d0d349 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -3677,6 +3677,52 @@
 		qcom,battery_debug {
 			compatible = "qcom,battery-debug";
 		};
+
+		spmi_glink_debug: qcom,spmi_glink_debug {
+			compatible = "qcom,spmi-glink-debug";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			/* Primary SPMI bus */
+			spmi@0 {
+				reg = <0>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				qcom,pm8350b-debug@3 {
+					compatible = "qcom,spmi-pmic";
+					reg = <0x3 SPMI_USID>;
+					qcom,can-sleep;
+				};
+			};
+
+			/* Secondary (QUP) SPMI bus */
+			spmi@1 {
+				reg = <1>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				qcom,smb1396-debug@b {
+					compatible = "qcom,spmi-pmic";
+					reg = <0xb SPMI_USID>;
+					qcom,can-sleep;
+				};
+
+				qcom,smb1396-debug@c {
+					compatible = "qcom,spmi-pmic";
+					reg = <0xc SPMI_USID>;
+					qcom,can-sleep;
+				};
+
+				smb1398_debug: qcom,smb1398-debug@d {
+					compatible = "qcom,spmi-pmic";
+					reg = <0xd SPMI_USID>;
+					qcom,can-sleep;
+					status = "disabled";
+				};
+			};
+		};
 	};
 
 	bluetooth: bt_qca6490 {