mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 07:37:31 -04:00
Merge "ARM: dts: msm: Add support for kgsl driver on SA6155"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
9ef578615a
4 changed files with 1331 additions and 0 deletions
338
qcom/sa6155.dtsi
338
qcom/sa6155.dtsi
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@ -61,3 +61,341 @@
|
|||
&slpi_tlmm {
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||||
status = "ok"
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||||
};
|
||||
|
||||
/* GPU power level overrides */
|
||||
&msm_gpu {
|
||||
/*
|
||||
* Speed-bin zero is default speed bin.
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||||
* For rest of the speed bins, speed-bin value
|
||||
* is calulated as FMAX/4.8 MHz round up to zero
|
||||
* decimal places.
|
||||
*/
|
||||
|
||||
/delete-node/qcom,gpu-pwrlevel-bins;
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
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||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@5 {
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||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <177>;
|
||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <156>;
|
||||
|
||||
qcom,initial-pwrlevel = <3>;
|
||||
qcom,ca-target-pwrlevel = <2>;
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <136>;
|
||||
|
||||
qcom,initial-pwrlevel = <2>;
|
||||
qcom,ca-target-pwrlevel = <1>;
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <105>;
|
||||
|
||||
qcom,initial-pwrlevel = <1>;
|
||||
qcom,ca-target-pwrlevel = <0>;
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <73>;
|
||||
|
||||
qcom,initial-pwrlevel = <0>;
|
||||
qcom,ca-target-pwrlevel = <0>;
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <350000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -79,3 +79,341 @@
|
|||
&slpi_tlmm {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
/* GPU power level overrides */
|
||||
&msm_gpu {
|
||||
/*
|
||||
* Speed-bin zero is default speed bin.
|
||||
* For rest of the speed bins, speed-bin value
|
||||
* is calulated as FMAX/4.8 MHz round up to zero
|
||||
* decimal places.
|
||||
*/
|
||||
|
||||
/delete-node/qcom,gpu-pwrlevel-bins;
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <177>;
|
||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <156>;
|
||||
|
||||
qcom,initial-pwrlevel = <3>;
|
||||
qcom,ca-target-pwrlevel = <2>;
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <136>;
|
||||
|
||||
qcom,initial-pwrlevel = <2>;
|
||||
qcom,ca-target-pwrlevel = <1>;
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <105>;
|
||||
|
||||
qcom,initial-pwrlevel = <1>;
|
||||
qcom,ca-target-pwrlevel = <0>;
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <73>;
|
||||
|
||||
qcom,initial-pwrlevel = <0>;
|
||||
qcom,ca-target-pwrlevel = <0>;
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <350000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
654
qcom/sm6150-gpu.dtsi
Normal file
654
qcom/sm6150-gpu.dtsi
Normal file
|
|
@ -0,0 +1,654 @@
|
|||
|
||||
#define KHZ_TO_KBPS(khz, w) ((khz * 1000 * w) / (1024))
|
||||
|
||||
&soc {
|
||||
pil_gpu: qcom,kgsl-hyp {
|
||||
compatible = "qcom,pil-tz-generic";
|
||||
qcom,pas-id = <13>;
|
||||
qcom,firmware-name = "a612_zap";
|
||||
memory-region = <&pil_gpu_mem>;
|
||||
};
|
||||
|
||||
msm_gpu: qcom,kgsl-3d0@5000000 {
|
||||
label = "kgsl-3d0";
|
||||
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
|
||||
status = "ok"
|
||||
reg = <0x5000000 0x90000>,
|
||||
<0x780000 0x6fff>;
|
||||
reg-names = "kgsl_3d0_reg_memory",
|
||||
"qfprom_memory";
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
qcom,id = <0>;
|
||||
|
||||
qcom,chipid = <0x06010200>;
|
||||
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
|
||||
/* <HZ/12> */
|
||||
qcom,idle-timeout = <80>;
|
||||
qcom,no-nap;
|
||||
|
||||
qcom,highest-bank-bit = <14>;
|
||||
qcom,ubwc-mode = <2>;
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
/* base addr, size */
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>;
|
||||
|
||||
clock-names = "core_clk", "rbbmtimer_clk", "gcc_gpu_axi_clk",
|
||||
"iface_clk", "gcc_gpu_memnoc_gfx",
|
||||
"gpu_cc_hlos1_vote_gpu_smmu", "gmu_clk";
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<KHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<KHZ_TO_KBPS(100000, 4)>, /* index=1 (Low SVS) */
|
||||
<KHZ_TO_KBPS(200000, 4)>, /* index=2 (Low SVS) */
|
||||
<KHZ_TO_KBPS(300000, 4)>, /* index=3 (Low SVS) */
|
||||
<KHZ_TO_KBPS(451200, 4)>, /* index=4 (Low SVS) */
|
||||
<KHZ_TO_KBPS(547200, 4)>, /* index=5 (Low SVS) */
|
||||
<KHZ_TO_KBPS(681600, 4)>, /* index=6 (SVS) */
|
||||
<KHZ_TO_KBPS(768000, 4)>, /* index=7 (SVS) */
|
||||
<KHZ_TO_KBPS(1017600, 4)>, /* index=8 (SVS L1) */
|
||||
<KHZ_TO_KBPS(1353600, 4)>, /* index=9 (NOM) */
|
||||
<KHZ_TO_KBPS(1555200, 4)>, /* index=10 (NOM) */
|
||||
<KHZ_TO_KBPS(1804800, 4)>; /* index=11 (TURBO) */
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
/* GDSC regulator names */
|
||||
regulator-names = "vddcx", "vdd";
|
||||
/* GDSC oxili regulators */
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
/* CPU latency parameter */
|
||||
qcom,pm-qos-active-latency = <67>;
|
||||
qcom,pm-qos-wakeup-latency = <67>;
|
||||
|
||||
/* Enable context aware freq. scaling */
|
||||
qcom,enable-ca-jump;
|
||||
/* Context aware jump busy penalty in us */
|
||||
qcom,ca-busy-penalty = <12000>;
|
||||
/* Context aware jump target power level */
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
qcom,gpu-speed-bin = <0x6004 0x1fe00000 21>;
|
||||
|
||||
/* GPU Mempools */
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Speed-bin zero is default speed bin.
|
||||
* For rest of the speed bins, speed-bin value
|
||||
* is calulated as FMAX/4.8 MHz round up to zero
|
||||
* decimal places.
|
||||
*/
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <700000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* Low SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <290000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <177>;
|
||||
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <700000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* Low SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <290000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <187>;
|
||||
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
qcom,ca-target-pwrlevel = <4>;
|
||||
|
||||
/* TURBO L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <895000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <700000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* Low SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <290000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <156>;
|
||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,ca-target-pwrlevel = <2>;
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <700000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* Low SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <290000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <136>;
|
||||
|
||||
qcom,initial-pwrlevel = <3>;
|
||||
qcom,ca-target-pwrlevel = <1>;
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* Low SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <290000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <105>;
|
||||
|
||||
qcom,initial-pwrlevel = <1>;
|
||||
qcom,ca-target-pwrlevel = <2>;
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* Low SVS */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <290000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <73>;
|
||||
|
||||
qcom,initial-pwrlevel = <1>;
|
||||
qcom,ca-target-pwrlevel = <0>;
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <350000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* Low SVS */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <290000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@0x050a0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
|
||||
reg = <0x050a0000 0x10000>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_user";
|
||||
iommus = <&kgsl_smmu 0x0 0x401>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_secure";
|
||||
iommus = <&kgsl_smmu 0x2 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
rgmu: qcom,rgmu@0x0506d000 {
|
||||
label = "kgsl-rgmu";
|
||||
compatible = "qcom,gpu-rgmu";
|
||||
|
||||
reg = <0x506d000 0x31000>;
|
||||
reg-names = "kgsl_rgmu";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_oob", "kgsl_rgmu";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gpucc GPU_CC_GX_GFX3D_CLK>;
|
||||
|
||||
clock-names = "gmu", "rbbmtimer", "mem",
|
||||
"iface", "mem_iface",
|
||||
"smmu_vote", "core";
|
||||
};
|
||||
};
|
||||
|
|
@ -2375,6 +2375,7 @@
|
|||
|
||||
#include "msm-arm-smmu-sm6150.dtsi"
|
||||
#include "sm6150-slpi-pinctrl.dtsi"
|
||||
#include "sm6150-gpu.dtsi"
|
||||
#include "sm6150-usb.dtsi"
|
||||
#include "sm6150-vidc.dtsi"
|
||||
#include "sm6150-ion.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in a new issue