From 9ef5a489ce77cc65d7e78fcdd8583f1998017abd Mon Sep 17 00:00:00 2001 From: Venkat Chinta Date: Mon, 3 Feb 2020 15:03:39 -0800 Subject: [PATCH] ARM: dts: msm: Add support for PHY-TPG in Lahaina and Bengal This change adds support for Camera CSI-PHY TPG hardware version 102. CRs-Fixed: 2608550 Change-Id: I220c2b0a7631568cff649a15c3e0511cc95ad4c7 --- bengal-camera.dtsi | 6 ++--- lahaina-camera.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 57 insertions(+), 4 deletions(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 7b2a6d944a47..f771d37433fb 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -773,7 +773,7 @@ cam_tfe_tpg0: qcom,tpg0@5c66000 { cell-index = <0>; - compatible = "qcom,tpgv1"; + compatible = "qcom,tpg101"; reg-names = "tpg0", "top"; reg = <0x5c66000 0x400>, <0x5c11000 0x1000>; @@ -796,9 +796,9 @@ status = "ok"; }; - cam_tfe_tpg1: qcom,tpg0@5c68000 { + cam_tfe_tpg1: qcom,tpg1@5c68000 { cell-index = <1>; - compatible = "qcom,tpgv1"; + compatible = "qcom,tpg101"; reg-names = "tpg0", "top"; reg = <0x5c68000 0x400>, <0x5c11000 0x1000>; diff --git a/lahaina-camera.dtsi b/lahaina-camera.dtsi index 53ef9e3f112c..0c24a25aa896 100644 --- a/lahaina-camera.dtsi +++ b/lahaina-camera.dtsi @@ -585,7 +585,8 @@ "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "custom0", "custom1", "ipe0", "cam-cdm-intf0", - "cpas-cdm0", "bps0", "icp0", "jpeg-dma0", "jpeg-enc0"; + "cpas-cdm0", "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", + "tpg0", "tpg1"; camera-bus-nodes { level3-nodes { @@ -1568,6 +1569,58 @@ status = "ok"; }; + cam_csiphy_tpg0: qcom,tpg0@ac97000 { + cell-index = <0>; + compatible = "qcom,tpg102"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xac97000 0x100>, + <0xac40000 0x1000>; + reg-cam-base = <0x97000 0x40000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-rates = + <400000000 0 300000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "csi0phytimer_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg1: qcom,tpg1@ac98000 { + cell-index = <1>; + compatible = "qcom,tpg102"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xac98000 0x100>, + <0xac40000 0x1000>; + reg-cam-base = <0x98000 0x40000>; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-rates = + <400000000 0 300000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "csi1phytimer_clk_src"; + status = "ok"; + }; + qcom,cam-icp { compatible = "qcom,cam-icp"; compat-hw-name = "qcom,a5",