From 9f1a2e9dedf3d2f744ac08de86fa6b5deda8040a Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 9 Feb 2021 23:41:27 +0530 Subject: [PATCH] mmc: core: Set the correct frequency when scaling down to DDR mode When scaling down to DDR mode we are passing 52Mhz to mmc_set_clock. The SDHC requires internal clock frequency to be double the actual clock that will be set for DDR mode. The controller uses the faster clock(100/400MHz) for some part of SDHC internal h/w logic and send the actual required clock (50/200MHz) to the card. So in sdhci_msm_set_clock we multiply the clock by 2 for DDR modes. Finally when we set host clk rate to 104Mhz then it scales to the nearest equal or larger value which is 192Mhz for sdcc1_apps clk as per clk drivers. High frequency of 192Mhz for DDR52 mode leads to CRC errors for some targets. Hence Set the frequency to 50Mhz instead of 52Mhz. Change-Id: I1d536db1dec4dfe16f41fd66362819c6db362901 Signed-off-by: Sarthak Garg --- drivers/mmc/core/mmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 87e76b37ff1a..f8d670055634 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1540,7 +1540,7 @@ static int mmc_hs200_tuning(struct mmc_card *card) } #if defined(CONFIG_SDC_QTI) -static int mmc_select_hs_ddr52(struct mmc_host *host) +static int mmc_select_hs_ddr52(struct mmc_host *host, unsigned long freq) { int err; @@ -1553,7 +1553,7 @@ static int mmc_select_hs_ddr52(struct mmc_host *host) } err = mmc_select_hs_ddr(host->card); - mmc_set_clock(host, MMC_HIGH_52_MAX_DTR); + mmc_set_clock(host, freq); return err; } @@ -1571,7 +1571,7 @@ static int mmc_scale_low(struct mmc_host *host, unsigned long freq) if (host->clk_scaling.lower_bus_speed_mode & MMC_SCALING_LOWER_DDR52_MODE) { - err = mmc_select_hs_ddr52(host); + err = mmc_select_hs_ddr52(host, freq); if (err) pr_err("%s: %s: failed to switch to DDR52: err: %d\n", mmc_hostname(host), __func__, err);