mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
Merge branch 'for-4.3-rc/ti-clk-fixes' of https://github.com/t-kristo/linux-pm into clk-fixes
Pull fixes from Tero Kristo: "A few TI clock driver fixes to pull against 4.3-rc" * 'for-4.3-rc/ti-clk-fixes' of https://github.com/t-kristo/linux-pm: (3 commits) clk: ti: dflt: fix enable_reg validity check clk: ti: fix dual-registration of uart4_ick clk: ti: clk-7xx: Remove hardwired ABE clock configuration
This commit is contained in:
Stephen Boyd
commit
9f30a04d76
10348 changed files with 566815 additions and 255819 deletions
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@ -381,6 +381,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
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clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
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clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
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clk[IMX6QDL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
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clk[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
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clk[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
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clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
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clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
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clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
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@ -126,7 +126,7 @@ PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
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PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
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PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
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#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENA : &CKENB)
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#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA)
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#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \
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div_hp, bit, is_lp, flags) \
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PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
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@ -780,6 +780,7 @@ static const char *const rk3288_critical_clocks[] __initconst = {
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"aclk_cpu",
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"aclk_peri",
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"hclk_peri",
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"pclk_pd_pmu",
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};
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#ifdef CONFIG_PM_SLEEP
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@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
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{ 0 },
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};
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static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
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{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
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{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
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{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
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{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
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{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
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{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
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{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
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{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
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{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
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{ 0 },
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};
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#define E4412_CPU_DIV1(cores, hpm, copy) \
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(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
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static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
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{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
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{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
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{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
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{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
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{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
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{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
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{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
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{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
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{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
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{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
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{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
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{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
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{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
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{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
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{ 0 },
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};
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/* register exynos4 clocks */
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static void __init exynos4_clk_init(struct device_node *np,
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enum exynos4_soc soc)
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@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node *np,
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samsung_clk_register_fixed_factor(ctx,
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exynos4x12_fixed_factor_clks,
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ARRAY_SIZE(exynos4x12_fixed_factor_clks));
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if (of_machine_is_compatible("samsung,exynos4412")) {
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
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CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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} else {
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
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CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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}
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}
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samsung_clk_register_alias(ctx, exynos4_aliases,
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@ -28,6 +28,8 @@
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#define USIBU1_RSTCTRL 0x0ac
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#define USIBU2_RSTCTRL 0x0b0
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#define USIBU3_RSTCTRL 0x0b4
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#define IIC0_RSTCTRL 0x0dc
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#define IIC1_RSTCTRL 0x0e0
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#define STI_RSTCTRL 0x124
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#define STI_CLKSEL 0x688
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@ -66,6 +68,10 @@ static void __init emev2_smu_init(void)
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emev2_smu_write(2, USIBU1_RSTCTRL);
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emev2_smu_write(2, USIBU2_RSTCTRL);
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emev2_smu_write(2, USIBU3_RSTCTRL);
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/* deassert reset for IIC0->IIC1 */
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emev2_smu_write(1, IIC0_RSTCTRL);
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emev2_smu_write(1, IIC1_RSTCTRL);
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}
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static void __init emev2_smu_clkdiv_init(struct device_node *np)
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@ -2,6 +2,7 @@
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* R-Car MSTP clocks
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*
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* Copyright (C) 2013 Ideas On Board SPRL
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* Copyright (C) 2015 Glider bvba
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*
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* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*
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@ -10,11 +11,16 @@
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/shmobile.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_domain.h>
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#include <linux/spinlock.h>
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/*
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@ -236,3 +242,84 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
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of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
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}
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CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
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#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
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int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
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{
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struct device_node *np = dev->of_node;
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struct of_phandle_args clkspec;
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struct clk *clk;
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int i = 0;
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int error;
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while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
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&clkspec)) {
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if (of_device_is_compatible(clkspec.np,
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"renesas,cpg-mstp-clocks"))
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goto found;
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of_node_put(clkspec.np);
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i++;
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}
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return 0;
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found:
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clk = of_clk_get_from_provider(&clkspec);
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of_node_put(clkspec.np);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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error = pm_clk_create(dev);
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if (error) {
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dev_err(dev, "pm_clk_create failed %d\n", error);
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goto fail_put;
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}
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error = pm_clk_add_clk(dev, clk);
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if (error) {
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dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
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goto fail_destroy;
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}
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return 0;
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fail_destroy:
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pm_clk_destroy(dev);
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fail_put:
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clk_put(clk);
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return error;
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}
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void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
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{
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if (!list_empty(&dev->power.subsys_data->clock_list))
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pm_clk_destroy(dev);
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}
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void __init cpg_mstp_add_clk_domain(struct device_node *np)
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{
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struct generic_pm_domain *pd;
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u32 ncells;
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if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
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pr_warn("%s lacks #power-domain-cells\n", np->full_name);
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return;
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}
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pd = kzalloc(sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return;
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|
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pd->name = np->name;
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pd->flags = GENPD_FLAG_PM_CLK;
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pm_genpd_init(pd, &simple_qos_governor, false);
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pd->attach_dev = cpg_mstp_attach_dev;
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pd->detach_dev = cpg_mstp_detach_dev;
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of_genpd_add_provider_simple(np, pd);
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}
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#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
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|
|
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|
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@ -124,6 +124,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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cpg_mstp_add_clk_domain(np);
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}
|
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|
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CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
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|
|
|
|||
|
|
@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
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|||
}
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||||
|
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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|
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cpg_mstp_add_clk_domain(np);
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}
|
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CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
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r8a7779_cpg_clocks_init);
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|
|
|
|||
|
|
@ -415,6 +415,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
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}
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|
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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|
||||
cpg_mstp_add_clk_domain(np);
|
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}
|
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CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
|
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rcar_gen2_cpg_clocks_init);
|
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|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/shmobile.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
|
|
@ -99,5 +100,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
|
|||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* Clock framework definitions for SPEAr platform
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* SPEAr1310 machine clock framework source file
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* SPEAr1340 machine clock framework source file
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* SPEAr3xx machines clock framework source file
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* SPEAr6xx machines clock framework source file
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -1210,6 +1210,7 @@ static void __init sun6i_init_clocks(struct device_node *node)
|
|||
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
|
||||
CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
|
||||
CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
|
||||
CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
|
||||
|
||||
static void __init sun9i_init_clocks(struct device_node *node)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ clk-common = dpll.o composite.o divider.o gate.o \
|
|||
fixed-factor.o mux.o apll.o \
|
||||
clkt_dpll.o clkt_iclk.o clkt_dflt.o
|
||||
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o
|
||||
obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
|
||||
obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
|
||||
obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
|
||||
clk-3xxx.o dpll3xxx.o
|
||||
|
|
|
|||
|
|
@ -374,7 +374,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
|
|||
DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
|
||||
DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
|
||||
DT_CLK(NULL, "uart3_ick", "uart3_ick"),
|
||||
DT_CLK(NULL, "uart4_ick", "uart4_ick"),
|
||||
DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
|
||||
DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
|
||||
DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
|
||||
|
|
@ -519,6 +518,7 @@ static struct ti_dt_clk am35xx_clks[] = {
|
|||
static struct ti_dt_clk omap36xx_clks[] = {
|
||||
DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
|
||||
DT_CLK(NULL, "uart4_fck", "uart4_fck"),
|
||||
DT_CLK(NULL, "uart4_ick", "uart4_ick"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ static struct ti_dt_clk am43xx_clks[] = {
|
|||
DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
|
||||
DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
|
||||
DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
|
||||
DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),
|
||||
DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
|
||||
DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
|
||||
#include "clock.h"
|
||||
|
||||
#define DRA7_DPLL_ABE_DEFFREQ 180633600
|
||||
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
|
||||
#define DRA7_DPLL_USB_DEFFREQ 960000000
|
||||
|
||||
|
|
@ -313,27 +312,12 @@ static struct ti_dt_clk dra7xx_clks[] = {
|
|||
int __init dra7xx_dt_clk_init(void)
|
||||
{
|
||||
int rc;
|
||||
struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *hdcp_ck;
|
||||
struct clk *dpll_ck, *hdcp_ck;
|
||||
|
||||
ti_dt_clocks_register(dra7xx_clks);
|
||||
|
||||
omap2_clk_disable_autoidle_all();
|
||||
|
||||
abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
|
||||
sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
|
||||
dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
|
||||
|
||||
rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
|
||||
if (!rc)
|
||||
rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
|
||||
|
||||
dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
|
||||
rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
|
||||
|
||||
dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
|
||||
rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
|
||||
if (rc)
|
||||
|
|
|
|||
33
drivers/clk/ti/clk-814x.c
Normal file
33
drivers/clk/ti/clk-814x.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
static struct ti_dt_clk dm814_clks[] = {
|
||||
DT_CLK(NULL, "devosc_ck", "devosc_ck"),
|
||||
DT_CLK(NULL, "mpu_ck", "mpu_ck"),
|
||||
DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
|
||||
DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
|
||||
DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
|
||||
DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
|
||||
DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
|
||||
DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
|
||||
DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
int __init dm814x_dt_clk_init(void)
|
||||
{
|
||||
ti_dt_clocks_register(dm814_clks);
|
||||
omap2_clk_disable_autoidle_all();
|
||||
omap2_clk_enable_init_clocks(NULL, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -44,7 +44,7 @@ static const char *enable_init_clks[] = {
|
|||
"ddr_pll_clk3",
|
||||
};
|
||||
|
||||
int __init ti81xx_dt_clk_init(void)
|
||||
int __init dm816x_dt_clk_init(void)
|
||||
{
|
||||
ti_dt_clocks_register(dm816x_clks);
|
||||
omap2_clk_disable_autoidle_all();
|
||||
|
|
|
|||
|
|
@ -222,7 +222,7 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
|
|||
}
|
||||
}
|
||||
|
||||
if (unlikely(!clk->enable_reg)) {
|
||||
if (unlikely(IS_ERR(clk->enable_reg))) {
|
||||
pr_err("%s: %s missing enable_reg\n", __func__,
|
||||
clk_hw_get_name(hw));
|
||||
ret = -EINVAL;
|
||||
|
|
@ -264,7 +264,7 @@ void omap2_dflt_clk_disable(struct clk_hw *hw)
|
|||
u32 v;
|
||||
|
||||
clk = to_clk_hw_omap(hw);
|
||||
if (!clk->enable_reg) {
|
||||
if (IS_ERR(clk->enable_reg)) {
|
||||
/*
|
||||
* 'independent' here refers to a clock which is not
|
||||
* controlled by its parent.
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
# Zynq clock specific Makefile
|
||||
|
||||
obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o
|
||||
obj-y += clkc.o pll.o
|
||||
|
|
|
|||
Loading…
Reference in a new issue