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msm: vidc: use clock-rates from static table instead from dtsi

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Currently video has multiple nodes in dtsi to support/limit
sw capabilities via sku-index. Mostly restriction comes in
terms of allowed-clock-rate. So created static entries in
platform.c to configure clocks based on plaform fuse value.
So that single vidc dtsi node is sufficient and there will
not be a probe defer/failure during bootup.

For ex. Shima supports 3 sku's.
AB - max 364.8 MHz - sku_version(1) - picked from dtsi(default sku)
AA - max 201.6 MHz - sku_version(2) - clock_data_v2
AC - max 444 MHz   - sku_version(0) - clock_data_v0(no fuse)

Single vidc node - "aa00000.qcom,vidc"

Change-Id: I870f1e3a24c0cbfdd92c537d3e40c4cf5400326d
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
This commit is contained in:
Govindaraj Rajagopal 2020-06-29 20:40:36 +05:30
commit 9f8094a79d
3 changed files with 30 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

2
msm/vidc/msm_vidc_internal.h
View file

@ -289,6 +289,8 @@ struct msm_vidc_platform_data {
unsigned int common_data_length;
struct msm_vidc_codec_data *codec_data;
unsigned int codec_data_length;
struct allowed_clock_rates_table *clock_data;
unsigned int clock_data_length;
struct msm_vidc_codec *codecs;
uint32_t codecs_count;
struct msm_vidc_codec_capability *codec_caps;

21
msm/vidc/msm_vidc_platform.c
View file

@ -726,6 +726,14 @@ static u32 vpe_csc_custom_limit_coeff[HAL_MAX_LIMIT_COEFFS] = {
16, 235, 16, 240, 16, 240
};
struct allowed_clock_rates_table shima_clock_data_v0[] = {
{240000000}, {338000000}, {366000000}, {444000000}
};
struct allowed_clock_rates_table shima_clock_data_v2[] = {
{201600000}
};
static struct msm_vidc_common_data default_common_data[] = {
{
.key = "qcom,never-unload-fw",
@ -1428,6 +1436,8 @@ static struct msm_vidc_platform_data default_data = {
static struct msm_vidc_platform_data lahaina_data = {
.codec_data = lahaina_codec_data,
.codec_data_length = ARRAY_SIZE(lahaina_codec_data),
.clock_data = NULL,
.clock_data_length = 0,
.common_data = lahaina_common_data,
.common_data_length = ARRAY_SIZE(lahaina_common_data),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
@ -1448,6 +1458,8 @@ static struct msm_vidc_platform_data lahaina_data = {
static struct msm_vidc_platform_data bengal_data = {
.codec_data = bengal_codec_data,
.codec_data_length = ARRAY_SIZE(bengal_codec_data),
.clock_data = NULL,
.clock_data_length = 0,
.common_data = bengal_common_data_v0,
.common_data_length = ARRAY_SIZE(bengal_common_data_v0),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
@ -1468,6 +1480,8 @@ static struct msm_vidc_platform_data bengal_data = {
static struct msm_vidc_platform_data shima_data = {
.codec_data = shima_codec_data,
.codec_data_length = ARRAY_SIZE(shima_codec_data),
.clock_data = shima_clock_data_v0,
.clock_data_length = ARRAY_SIZE(shima_clock_data_v0),
.common_data = shima_common_data_v0,
.common_data_length = ARRAY_SIZE(shima_common_data_v0),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
@ -1488,6 +1502,8 @@ static struct msm_vidc_platform_data shima_data = {
static struct msm_vidc_platform_data holi_data = {
.codec_data = holi_codec_data,
.codec_data_length = ARRAY_SIZE(holi_codec_data),
.clock_data = NULL,
.clock_data_length = 0,
.common_data = holi_common_data,
.common_data_length = ARRAY_SIZE(holi_common_data),
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
@ -1641,6 +1657,8 @@ void *vidc_get_drv_data(struct device *dev)
}
} else if (!strcmp(match->compatible, "qcom,shima-vidc")) {
if (driver_data->sku_version == SKU_VERSION_1) {
driver_data->clock_data = NULL;
driver_data->clock_data_length = 0;
driver_data->common_data = shima_common_data_v1;
driver_data->common_data_length =
ARRAY_SIZE(shima_common_data_v1);
@ -1648,6 +1666,9 @@ void *vidc_get_drv_data(struct device *dev)
driver_data->codec_caps_count =
ARRAY_SIZE(shima_capabilities_v1);
} else if (driver_data->sku_version == SKU_VERSION_2) {
driver_data->clock_data = shima_clock_data_v2;
driver_data->clock_data_length =
ARRAY_SIZE(shima_clock_data_v2);
driver_data->common_data = shima_common_data_v2;
driver_data->common_data_length =
ARRAY_SIZE(shima_common_data_v2);

34
msm/vidc/msm_vidc_res_parse.c
View file

@ -347,6 +347,11 @@ static int msm_vidc_load_allowed_clocks_table(
int rc = 0;
struct platform_device *pdev = res->pdev;
if (res->allowed_clks_tbl) {
d_vpr_h("allowed-clock-rates populated from platform_data\n");
return 0;
}
if (!of_find_property(pdev->dev.of_node,
"qcom,allowed-clock-rates", NULL)) {
d_vpr_h("allowed-clock-rates not found\n");
@ -692,29 +697,6 @@ static int msm_vidc_load_reset_table(
return 0;
}
static int msm_decide_dt_node(
struct msm_vidc_platform_resources *res)
{
struct platform_device *pdev = res->pdev;
int rc = 0;
u32 sku_index = 0;
rc = of_property_read_u32(pdev->dev.of_node, "sku-index",
&sku_index);
if (rc) {
d_vpr_h("'sku_index' not found in node\n");
return 0;
}
if (sku_index != res->sku_version) {
d_vpr_h("Failed to parse dt: sku_index %d sku_version %d\n",
sku_index, res->sku_version);
return -EINVAL;
}
return 0;
}
static int find_key_value(struct msm_vidc_platform_data *platform_data,
const char *key)
{
@ -749,6 +731,8 @@ int read_platform_resources_from_drv_data(
res->codec_caps_count = platform_data->codec_caps_count;
res->codec_data_count = platform_data->codec_data_length;
res->codec_data = platform_data->codec_data;
res->allowed_clks_tbl = platform_data->clock_data;
res->allowed_clks_tbl_size = platform_data->clock_data_length;
res->sku_version = platform_data->sku_version;
res->mem_limit_tbl = memory_limit_tbl_mbytes;
@ -852,10 +836,6 @@ int read_platform_resources_from_dt(
return -ENOENT;
}
rc = msm_decide_dt_node(res);
if (rc)
return rc;
INIT_LIST_HEAD(&res->context_banks);
res->firmware_base = (phys_addr_t)firmware_base;