From eefcfb1cd26e8099c8f8da44c3393164d6deab54 Mon Sep 17 00:00:00 2001 From: Kogara Naveen Kumar Date: Tue, 31 May 2022 14:56:09 +0530 Subject: [PATCH] audio-kernal: Loading only Gen3 specific mixer controls for Gen3 boards Changes to prevent loading of Gen4 specific mixer controls on Gen3 boards. Change-Id: I851da6feb75a0fc2080ed37853312b779b946c40 --- asoc/msm-pcm-routing-auto.c | 2816 ++++++++++++++++++----------------- 1 file changed, 1435 insertions(+), 1381 deletions(-) diff --git a/asoc/msm-pcm-routing-auto.c b/asoc/msm-pcm-routing-auto.c index b2e993e65a49..08fb1fbb47ca 100644 --- a/asoc/msm-pcm-routing-auto.c +++ b/asoc/msm-pcm-routing-auto.c @@ -9376,7 +9376,7 @@ static const struct snd_kcontrol_new quin_tdm_rx_3_mixer_controls[] = { MSM_FRONTEND_DAI_MULTIMEDIA34, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; - +//Gen4 specific mixer controls start static const struct snd_kcontrol_new sen_tdm_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_TDM_RX_0, @@ -12140,7 +12140,7 @@ static const struct snd_kcontrol_new hsif2_tdm_rx_7_mixer_controls[] = { MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; - +//Gen4 specific mixer controls ends static const struct snd_kcontrol_new pri_tdm_rx_0_port_mixer_controls[] = { #ifndef CONFIG_MI2S_DISABLE @@ -14602,7 +14602,7 @@ static const struct snd_kcontrol_new quin_tdm_rx_3_port_mixer_controls[] = { msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; - +//Gen4 specific mixer controls start static const struct snd_kcontrol_new sen_tdm_rx_0_port_mixer_controls[] = { #ifndef CONFIG_MI2S_DISABLE SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, @@ -19024,6 +19024,7 @@ static const struct snd_kcontrol_new hsif2_tdm_rx_7_port_mixer_controls[] = { msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; +//Gen4 specific mixer controls ends static const struct snd_kcontrol_new quin_tdm_rx_7_port_mixer_controls[] = { SOC_DOUBLE_EXT("TERT_TDM_TX_7", SND_SOC_NOPM, @@ -26104,6 +26105,305 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets_tdm[] = { SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_7_UL_HL", "Quinary TDM7 Hostless Capture", 0, 0, 0, 0), + /* Backend AIF */ + /* Stream name equals to backend dai link stream name */ + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_0", "Primary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_0", "Primary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_1", "Primary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_1", "Primary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_2", "Primary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_2", "Primary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_3", "Primary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_3", "Primary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_4", "Primary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_4", "Primary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_5", "Primary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_5", "Primary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_6", "Primary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_6", "Primary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_7", "Primary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_7", "Primary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_0", "Secondary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_0", "Secondary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_1", "Secondary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_1", "Secondary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_2", "Secondary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_2", "Secondary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_3", "Secondary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_3", "Secondary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_4", "Secondary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_4", "Secondary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_5", "Secondary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_5", "Secondary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_6", "Secondary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_6", "Secondary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_7", "Secondary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_7", "Secondary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_0", "Tertiary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_0", "Tertiary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_1", "Tertiary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_1", "Tertiary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_2", "Tertiary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_2", "Tertiary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_3", "Tertiary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_3", "Tertiary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_4", "Tertiary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_4", "Tertiary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_5", "Tertiary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_5", "Tertiary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_6", "Tertiary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_6", "Tertiary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_7", "Tertiary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_7", "Tertiary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_0", "Quaternary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_0", "Quaternary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_1", "Quaternary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_1", "Quaternary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_2", "Quaternary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_2", "Quaternary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_3", "Quaternary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_3", "Quaternary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_4", "Quaternary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_4", "Quaternary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_5", "Quaternary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_5", "Quaternary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_6", "Quaternary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_6", "Quaternary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_7", "Quaternary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_7", "Quaternary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_0", "Quinary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_0", "Quinary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_1", "Quinary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_1", "Quinary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_2", "Quinary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_2", "Quinary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_3", "Quinary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_3", "Quinary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_4", "Quinary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_4", "Quinary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_5", "Quinary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_5", "Quinary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_6", "Quinary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_6", "Quinary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_7", "Quinary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_7", "Quinary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_0_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_1_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_2_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_3_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_0_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_1_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_2_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_3_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_0_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_1_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_2_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_3_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_4_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_4_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_0_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_1_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_2_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_3_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_0_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_1_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_2_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_3_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_3_mixer_controls)), + /* incall */ + SND_SOC_DAPM_MIXER("PRI_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_0_port_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_0_port_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_1_port_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_1_port_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_2_port_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_2_port_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_3_port_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_3_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_0_port_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_0_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_1_port_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_1_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_2_port_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_2_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_3_port_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_3_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_7 Port Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_7_port_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_7_port_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_0_port_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_0_port_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_1_port_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_1_port_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_2_port_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_2_port_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_3_port_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_3_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_0_port_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_0_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_1_port_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_1_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_2_port_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_2_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_3_port_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_3_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_7 Port Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_7_port_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_7_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_0_port_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_0_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_1_port_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_1_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_2_port_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_2_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_3_port_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_3_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_7 Port Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_7_port_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_7_port_mixer_controls)), +}; + +static const struct snd_soc_dapm_widget msm_qdsp6_widgets_tdm_gen4[] = { + SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_0_DL_HL", "Senary TDM0 Hostless Playback", 0, 0, 0, 0), @@ -26345,168 +26645,6 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets_tdm[] = { "Hsif2 TDM7 Hostless Capture", 0, 0, 0, 0), - /* Backend AIF */ - /* Stream name equals to backend dai link stream name */ - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_0", "Primary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_0", "Primary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_1", "Primary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_1", "Primary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_2", "Primary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_2", "Primary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_3", "Primary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_3", "Primary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_4", "Primary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_4", "Primary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_5", "Primary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_5", "Primary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_6", "Primary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_6", "Primary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_7", "Primary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_7", "Primary TDM7 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_0", "Secondary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_0", "Secondary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_1", "Secondary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_1", "Secondary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_2", "Secondary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_2", "Secondary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_3", "Secondary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_3", "Secondary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_4", "Secondary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_4", "Secondary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_5", "Secondary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_5", "Secondary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_6", "Secondary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_6", "Secondary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_7", "Secondary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_7", "Secondary TDM7 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_0", "Tertiary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_0", "Tertiary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_1", "Tertiary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_1", "Tertiary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_2", "Tertiary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_2", "Tertiary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_3", "Tertiary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_3", "Tertiary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_4", "Tertiary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_4", "Tertiary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_5", "Tertiary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_5", "Tertiary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_6", "Tertiary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_6", "Tertiary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_7", "Tertiary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_7", "Tertiary TDM7 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_0", "Quaternary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_0", "Quaternary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_1", "Quaternary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_1", "Quaternary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_2", "Quaternary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_2", "Quaternary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_3", "Quaternary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_3", "Quaternary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_4", "Quaternary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_4", "Quaternary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_5", "Quaternary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_5", "Quaternary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_6", "Quaternary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_6", "Quaternary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_7", "Quaternary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_7", "Quaternary TDM7 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_0", "Quinary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_0", "Quinary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_1", "Quinary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_1", "Quinary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_2", "Quinary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_2", "Quinary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_3", "Quinary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_3", "Quinary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_4", "Quinary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_4", "Quinary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_5", "Quinary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_5", "Quinary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_6", "Quinary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_6", "Quinary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_7", "Quinary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_7", "Quinary TDM7 Capture", - 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_0", "Senary TDM0 Playback", 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_0", "Senary TDM0 Capture", @@ -26668,69 +26806,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets_tdm[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("HSIF2_TDM_TX_7", "Hsif2 TDM7 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_0_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_1_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_2_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_3_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_0_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_1_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_2_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_3_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_0_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_1_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_2_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_3_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_4_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_4_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_0_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_1_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_2_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_3_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_0_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_1_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_2_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_3_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, sen_tdm_rx_0_mixer_controls, ARRAY_SIZE(sen_tdm_rx_0_mixer_controls)), @@ -26839,76 +26915,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets_tdm[] = { SND_SOC_DAPM_MIXER("HSIF2_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0, hsif2_tdm_rx_7_mixer_controls, ARRAY_SIZE(hsif2_tdm_rx_7_mixer_controls)), - /* incall */ - SND_SOC_DAPM_MIXER("PRI_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_0_port_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_0_port_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_1_port_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_1_port_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_2_port_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_2_port_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_3_port_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_3_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_0_port_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_0_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_1_port_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_1_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_2_port_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_2_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_3_port_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_3_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_7 Port Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_7_port_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_7_port_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_0_port_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_0_port_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_1_port_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_1_port_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_2_port_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_2_port_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_3_port_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_3_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_0_port_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_0_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_1_port_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_1_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_2_port_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_2_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_3_port_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_3_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_7 Port Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_7_port_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_7_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_0_port_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_0_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_1_port_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_1_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2 Port Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_2_port_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_2_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_3_port_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_3_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_7 Port Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_7_port_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_7_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, sen_tdm_rx_0_port_mixer_controls, ARRAY_SIZE(sen_tdm_rx_0_port_mixer_controls)), @@ -28005,6 +28012,1107 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia34", "MM_DL34"}, {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3 Audio Mixer"}, + {"MultiMedia1 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia1 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia1 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia1 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia1 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia1 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia1 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia1 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia1 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia1 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia1 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia1 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia1 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia1 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia1 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + + {"MultiMedia1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia1 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia1 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia1 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia2 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia2 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia2 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia2 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia2 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia2 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia2 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia2 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia2 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia2 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia2 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia2 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia2 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia2 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia2 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia2 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia2 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia2 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia2 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia2 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia3 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia3 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia3 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia3 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia3 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia3 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia3 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia3 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia3 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia3 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia3 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia3 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia3 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia3 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia3 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia3 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia3 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia3 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia3 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia3 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia4 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia4 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia4 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia4 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia4 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia4 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia4 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia4 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia4 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia4 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia4 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia4 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia4 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia4 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia4 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia4 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia4 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia4 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia4 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia4 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia5 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia5 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia5 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia5 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia5 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia5 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia5 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia5 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia5 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia5 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia5 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia5 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia5 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia5 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia5 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia5 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia5 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia5 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia5 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia5 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia8 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia8 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia8 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia8 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia8 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia8 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia8 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia8 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia8 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia8 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia8 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia8 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia8 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia8 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia8 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia8 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia8 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia8 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia8 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia8 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia9 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia9 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia9 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia9 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia9 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia9 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia9 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia9 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia9 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia9 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia9 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia9 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia10 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia10 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia10 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia10 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia10 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia10 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia10 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia10 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + + {"MultiMedia17 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + + {"MultiMedia20 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia20 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia20 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia20 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia20 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia20 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia20 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia20 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia20 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia20 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia20 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia20 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia20 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia20 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia20 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia20 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia20 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia20 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia20 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia20 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia21 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia21 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia21 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia21 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia21 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia21 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia21 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia21 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia21 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia21 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia21 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia21 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia21 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia21 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia21 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia21 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia21 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia21 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia21 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia21 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia22 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia22 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia22 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia22 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia22 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia22 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia22 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia22 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia22 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia22 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia22 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia22 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia22 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia22 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia22 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia22 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia22 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia22 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia22 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia22 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia23 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia23 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia23 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia23 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia23 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia23 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia23 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia23 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia23 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia23 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia23 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia23 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia23 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia23 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia23 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia23 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia23 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia23 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia23 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia23 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia24 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia24 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia24 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia24 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia24 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia24 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia24 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia24 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia24 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia24 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia24 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia24 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia24 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia24 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia24 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia24 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia24 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia24 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia24 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia24 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia25 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia25 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia25 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia25 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia25 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia25 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia25 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia25 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia25 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia25 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia25 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia25 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia25 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia25 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia25 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia25 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia25 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia25 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia25 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia25 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia31 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia31 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia31 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia31 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia31 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia31 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia31 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia31 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia31 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia31 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia31 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia31 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia31 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia31 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia31 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia31 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia31 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia31 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia31 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia31 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia32 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia32 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia32 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia32 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia32 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia32 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia32 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia32 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia32 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia32 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia32 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia32 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia32 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia32 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia32 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia32 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia32 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia32 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia32 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia32 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia33 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia33 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia33 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia33 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia33 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia33 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia33 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia33 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia33 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia33 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia33 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia33 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia33 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia33 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia33 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia33 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia33 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia33 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia33 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia33 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + {"MultiMedia34 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia34 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia34 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia34 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia34 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia34 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia34 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia34 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia34 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia34 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia34 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia34 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia34 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia34 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia34 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia34 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia34 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia34 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia34 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia34 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + + /* connect to INT4_MI2S_DL_HL since same pcm_id */ + {"PRI_TDM_TX_0_UL_HL", NULL, "PRI_TDM_TX_0"}, + {"PRI_TDM_TX_1_UL_HL", NULL, "PRI_TDM_TX_1"}, + {"PRI_TDM_TX_2_UL_HL", NULL, "PRI_TDM_TX_2"}, + {"PRI_TDM_TX_3_UL_HL", NULL, "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0_DL_HL"}, + {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1_DL_HL"}, + {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2_DL_HL"}, + {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3_DL_HL"}, + {"SEC_TDM_TX_0_UL_HL", NULL, "SEC_TDM_TX_0"}, + {"SEC_TDM_TX_1_UL_HL", NULL, "SEC_TDM_TX_1"}, + {"SEC_TDM_TX_2_UL_HL", NULL, "SEC_TDM_TX_2"}, + {"SEC_TDM_TX_3_UL_HL", NULL, "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0_DL_HL"}, + {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1_DL_HL"}, + {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2_DL_HL"}, + {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3_DL_HL"}, + {"SEC_TDM_RX_7", NULL, "SEC_TDM_RX_7_DL_HL"}, + {"TERT_TDM_TX_0_UL_HL", NULL, "TERT_TDM_TX_0"}, + {"TERT_TDM_TX_1_UL_HL", NULL, "TERT_TDM_TX_1"}, + {"TERT_TDM_TX_2_UL_HL", NULL, "TERT_TDM_TX_2"}, + {"TERT_TDM_TX_3_UL_HL", NULL, "TERT_TDM_TX_3"}, + {"TERT_TDM_TX_7_UL_HL", NULL, "TERT_TDM_TX_7"}, + {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0_DL_HL"}, + {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1_DL_HL"}, + {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2_DL_HL"}, + {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3_DL_HL"}, + {"QUAT_TDM_TX_0_UL_HL", NULL, "QUAT_TDM_TX_0"}, + {"QUAT_TDM_TX_1_UL_HL", NULL, "QUAT_TDM_TX_1"}, + {"QUAT_TDM_TX_2_UL_HL", NULL, "QUAT_TDM_TX_2"}, + {"QUAT_TDM_TX_3_UL_HL", NULL, "QUAT_TDM_TX_3"}, + {"QUAT_TDM_TX_7_UL_HL", NULL, "QUAT_TDM_TX_7"}, + {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0_DL_HL"}, + {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1_DL_HL"}, + {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2_DL_HL"}, + {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3_DL_HL"}, + {"QUAT_TDM_RX_7", NULL, "QUAT_TDM_RX_7_DL_HL"}, + {"QUIN_TDM_TX_0_UL_HL", NULL, "QUIN_TDM_TX_0"}, + {"QUIN_TDM_TX_1_UL_HL", NULL, "QUIN_TDM_TX_1"}, + {"QUIN_TDM_TX_2_UL_HL", NULL, "QUIN_TDM_TX_2"}, + {"QUIN_TDM_TX_3_UL_HL", NULL, "QUIN_TDM_TX_3"}, + {"QUIN_TDM_TX_7_UL_HL", NULL, "QUIN_TDM_TX_7"}, + {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0_DL_HL"}, + {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1_DL_HL"}, + {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2_DL_HL"}, + {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3_DL_HL"}, + {"QUIN_TDM_RX_7", NULL, "QUIN_TDM_RX_7_DL_HL"}, + +#ifndef CONFIG_MI2S_DISABLE + {"PRI_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"PRI_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"PRI_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"PRI_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"PRI_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"PRI_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"PRI_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"PRI_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"PRI_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"PRI_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"PRI_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"PRI_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"PRI_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"PRI_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"PRI_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"PRI_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"PRI_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"PRI_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"PRI_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"PRI_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"PRI_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"PRI_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"PRI_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"PRI_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"SEC_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"SEC_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEC_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEC_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"SEC_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"SEC_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEC_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEC_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"SEC_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"SEC_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEC_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEC_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"SEC_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"SEC_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEC_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEC_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3 Port Mixer"}, + + {"SEC_TDM_RX_7 Port Mixer", "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, + {"SEC_TDM_RX_7", NULL, "SEC_TDM_RX_7 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"TERT_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"TERT_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"TERT_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"TERT_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"TERT_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"TERT_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"TERT_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"TERT_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"TERT_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"TERT_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"TERT_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"TERT_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"TERT_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"TERT_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"TERT_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"TERT_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"TERT_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"TERT_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"TERT_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"TERT_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"TERT_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"TERT_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"TERT_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"TERT_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"QUAT_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUAT_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUAT_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUAT_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUAT_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"QUAT_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUAT_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUAT_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUAT_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUAT_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"QUAT_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUAT_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUAT_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUAT_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUAT_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"QUAT_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUAT_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUAT_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUAT_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUAT_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3 Port Mixer"}, + + {"QUAT_TDM_RX_7 Port Mixer", "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, + {"QUAT_TDM_RX_7 Port Mixer", "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}, + {"QUAT_TDM_RX_7", NULL, "QUAT_TDM_RX_7 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"QUIN_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUIN_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUIN_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUIN_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUIN_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"QUIN_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUIN_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUIN_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUIN_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUIN_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"QUIN_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUIN_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUIN_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUIN_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUIN_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"QUIN_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUIN_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUIN_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUIN_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUIN_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3 Port Mixer"}, + + {"QUIN_TDM_RX_7 Port Mixer", "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, + {"QUIN_TDM_RX_7 Port Mixer", "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, + {"QUIN_TDM_RX_7 Port Mixer", "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}, + {"QUIN_TDM_RX_7", NULL, "QUIN_TDM_RX_7 Port Mixer"}, + + {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_0", "QUAT_TDM_RX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_1", "QUAT_TDM_RX_1"}, + {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_2", "QUAT_TDM_RX_2"}, + {"AUDIO_REF_EC_UL1 MUX", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "TERT_TDM_RX_2", "TERT_TDM_RX_2"}, + {"AUDIO_REF_EC_UL1 MUX", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "PRI_TDM_RX_0", "PRI_TDM_RX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + + {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_0", "QUAT_TDM_RX_0"}, + {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_1", "QUAT_TDM_RX_1"}, + {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_2", "QUAT_TDM_RX_2"}, + {"AUDIO_REF_EC_UL10 MUX", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"AUDIO_REF_EC_UL10 MUX", "TERT_TDM_RX_2", "TERT_TDM_RX_2"}, + {"AUDIO_REF_EC_UL10 MUX", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"AUDIO_REF_EC_UL10 MUX", "PRI_TDM_RX_0", "PRI_TDM_RX_0"}, + {"AUDIO_REF_EC_UL10 MUX", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + + {"LSM1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM2 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM2 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM3 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM3 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM4 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM4 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM5 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM5 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM6 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM6 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM7 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM7 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM8 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM8 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + + {"LSM1 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"LSM2 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"LSM3 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"LSM4 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"LSM5 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"LSM6 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"LSM7 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"LSM8 Mixer", "AFE_PCM_TX", "PCM_TX"}, + + /* Backend Enablement */ + {"BE_OUT", NULL, "PRI_TDM_RX_0"}, + {"BE_OUT", NULL, "PRI_TDM_RX_1"}, + {"BE_OUT", NULL, "PRI_TDM_RX_2"}, + {"BE_OUT", NULL, "PRI_TDM_RX_3"}, + {"BE_OUT", NULL, "SEC_TDM_RX_0"}, + {"BE_OUT", NULL, "SEC_TDM_RX_1"}, + {"BE_OUT", NULL, "SEC_TDM_RX_2"}, + {"BE_OUT", NULL, "SEC_TDM_RX_3"}, + {"BE_OUT", NULL, "SEC_TDM_RX_7"}, + {"BE_OUT", NULL, "TERT_TDM_RX_0"}, + {"BE_OUT", NULL, "TERT_TDM_RX_1"}, + {"BE_OUT", NULL, "TERT_TDM_RX_2"}, + {"BE_OUT", NULL, "TERT_TDM_RX_3"}, + {"BE_OUT", NULL, "TERT_TDM_RX_4"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_0"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_1"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_2"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_3"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_7"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_0"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_1"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_2"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_3"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_7"}, + + {"PRI_TDM_TX_0", NULL, "BE_IN"}, + {"PRI_TDM_TX_1", NULL, "BE_IN"}, + {"PRI_TDM_TX_2", NULL, "BE_IN"}, + {"PRI_TDM_TX_3", NULL, "BE_IN"}, + {"SEC_TDM_TX_0", NULL, "BE_IN"}, + {"SEC_TDM_TX_1", NULL, "BE_IN"}, + {"SEC_TDM_TX_2", NULL, "BE_IN"}, + {"SEC_TDM_TX_3", NULL, "BE_IN"}, + {"TERT_TDM_TX_0", NULL, "BE_IN"}, + {"TERT_TDM_TX_1", NULL, "BE_IN"}, + {"TERT_TDM_TX_2", NULL, "BE_IN"}, + {"TERT_TDM_TX_3", NULL, "BE_IN"}, + {"TERT_TDM_TX_7", NULL, "BE_IN"}, + {"QUAT_TDM_TX_0", NULL, "BE_IN"}, + {"QUAT_TDM_TX_1", NULL, "BE_IN"}, + {"QUAT_TDM_TX_2", NULL, "BE_IN"}, + {"QUAT_TDM_TX_3", NULL, "BE_IN"}, + {"QUAT_TDM_TX_7", NULL, "BE_IN"}, + {"QUIN_TDM_TX_0", NULL, "BE_IN"}, + {"QUIN_TDM_TX_1", NULL, "BE_IN"}, + {"QUIN_TDM_TX_2", NULL, "BE_IN"}, + {"QUIN_TDM_TX_3", NULL, "BE_IN"}, + {"QUIN_TDM_TX_7", NULL, "BE_IN"}, + +}; + +static const struct snd_soc_dapm_route intercon_tdm_gen4[] = { {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, @@ -28701,27 +29809,7 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"HSIF2_TDM_RX_7 Audio Mixer", "MultiMedia20", "MM_DL20"}, {"HSIF2_TDM_RX_7 Audio Mixer", "MultiMedia21", "MM_DL21"}, {"HSIF2_TDM_RX_7", NULL, "HSIF2_TDM_RX_7 Audio Mixer"}, - {"MultiMedia1 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia1 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia1 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia1 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia1 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia1 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia1 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia1 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia1 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia1 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia1 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia1 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia1 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia1 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia1 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia1 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia1 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia1 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, {"MultiMedia1 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, {"MultiMedia1 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia1 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, @@ -28759,26 +29847,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"MultiMedia1 Mixer", "HSIF2_TDM_TX_6", "HSIF2_TDM_TX_6"}, {"MultiMedia1 Mixer", "HSIF2_TDM_TX_7", "HSIF2_TDM_TX_7"}, - {"MultiMedia2 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia2 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia2 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia2 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia2 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia2 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia2 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia2 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia2 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia2 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia2 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia2 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia2 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia2 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia2 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia2 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia2 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia2 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia2 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia2 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, {"MultiMedia2 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, {"MultiMedia2 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia2 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, @@ -28816,26 +29884,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"MultiMedia2 Mixer", "HSIF2_TDM_TX_6", "HSIF2_TDM_TX_6"}, {"MultiMedia2 Mixer", "HSIF2_TDM_TX_7", "HSIF2_TDM_TX_7"}, - {"MultiMedia3 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia3 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia3 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia3 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia3 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia3 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia3 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia3 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia3 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia3 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia3 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia3 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia3 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia3 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia3 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia3 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia3 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia3 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia3 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia3 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, {"MultiMedia3 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, {"MultiMedia3 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia3 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, @@ -28873,26 +29921,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"MultiMedia3 Mixer", "HSIF2_TDM_TX_6", "HSIF2_TDM_TX_6"}, {"MultiMedia3 Mixer", "HSIF2_TDM_TX_7", "HSIF2_TDM_TX_7"}, - {"MultiMedia4 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia4 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia4 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia4 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia4 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia4 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia4 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia4 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia4 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia4 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia4 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia4 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia4 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia4 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia4 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia4 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia4 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia4 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia4 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia4 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, {"MultiMedia4 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, {"MultiMedia4 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia4 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, @@ -28930,26 +29958,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"MultiMedia4 Mixer", "HSIF2_TDM_TX_6", "HSIF2_TDM_TX_6"}, {"MultiMedia4 Mixer", "HSIF2_TDM_TX_7", "HSIF2_TDM_TX_7"}, - {"MultiMedia5 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia5 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia5 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia5 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia5 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia5 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia5 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia5 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia5 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia5 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia5 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia5 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia5 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia5 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia5 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia5 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia5 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia5 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia5 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia5 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, {"MultiMedia5 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, {"MultiMedia5 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia5 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, @@ -28987,26 +29995,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"MultiMedia5 Mixer", "HSIF2_TDM_TX_6", "HSIF2_TDM_TX_6"}, {"MultiMedia5 Mixer", "HSIF2_TDM_TX_7", "HSIF2_TDM_TX_7"}, - {"MultiMedia8 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia8 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia8 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia8 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia8 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia8 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia8 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia8 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia8 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia8 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia8 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia8 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia8 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia8 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia8 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia8 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia8 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia8 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia8 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia8 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, {"MultiMedia8 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, {"MultiMedia8 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia8 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, @@ -29044,18 +30032,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"MultiMedia8 Mixer", "HSIF2_TDM_TX_6", "HSIF2_TDM_TX_6"}, {"MultiMedia8 Mixer", "HSIF2_TDM_TX_7", "HSIF2_TDM_TX_7"}, - {"MultiMedia9 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia9 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia9 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia9 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia9 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia9 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia9 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia9 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia9 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia9 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia9 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia9 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, {"MultiMedia9 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, {"MultiMedia9 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia9 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, @@ -29093,37 +30069,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"MultiMedia9 Mixer", "HSIF2_TDM_TX_6", "HSIF2_TDM_TX_6"}, {"MultiMedia9 Mixer", "HSIF2_TDM_TX_7", "HSIF2_TDM_TX_7"}, - {"MultiMedia10 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia10 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia10 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia10 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia10 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia10 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia10 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia10 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - - {"MultiMedia17 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - - {"MultiMedia20 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia20 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia20 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia20 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia20 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia20 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia20 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia20 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia20 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia20 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia20 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia20 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia20 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia20 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia20 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia20 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia20 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia20 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia20 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia20 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, {"MultiMedia20 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, {"MultiMedia20 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia20 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, @@ -29161,26 +30106,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"MultiMedia20 Mixer", "HSIF2_TDM_TX_6", "HSIF2_TDM_TX_6"}, {"MultiMedia20 Mixer", "HSIF2_TDM_TX_7", "HSIF2_TDM_TX_7"}, - {"MultiMedia21 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia21 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia21 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia21 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia21 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia21 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia21 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia21 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia21 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia21 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia21 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia21 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia21 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia21 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia21 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia21 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia21 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia21 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia21 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia21 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, {"MultiMedia21 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, {"MultiMedia21 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia21 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, @@ -29218,221 +30143,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"MultiMedia21 Mixer", "HSIF2_TDM_TX_6", "HSIF2_TDM_TX_6"}, {"MultiMedia21 Mixer", "HSIF2_TDM_TX_7", "HSIF2_TDM_TX_7"}, - {"MultiMedia22 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia22 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia22 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia22 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia22 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia22 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia22 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia22 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia22 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia22 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia22 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia22 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia22 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia22 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia22 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia22 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia22 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia22 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia22 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia22 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - - {"MultiMedia23 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia23 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia23 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia23 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia23 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia23 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia23 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia23 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia23 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia23 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia23 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia23 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia23 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia23 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia23 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia23 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia23 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia23 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia23 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia23 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - - {"MultiMedia24 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia24 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia24 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia24 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia24 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia24 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia24 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia24 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia24 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia24 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia24 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia24 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia24 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia24 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia24 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia24 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia24 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia24 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia24 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia24 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - - {"MultiMedia25 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia25 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia25 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia25 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia25 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia25 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia25 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia25 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia25 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia25 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia25 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia25 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia25 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia25 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia25 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia25 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia25 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia25 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia25 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia25 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - - {"MultiMedia31 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia31 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia31 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia31 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia31 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia31 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia31 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia31 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia31 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia31 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia31 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia31 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia31 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia31 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia31 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia31 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia31 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia31 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia31 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia31 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - - {"MultiMedia32 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia32 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia32 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia32 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia32 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia32 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia32 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia32 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia32 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia32 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia32 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia32 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia32 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia32 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia32 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia32 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia32 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia32 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia32 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia32 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - - {"MultiMedia33 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia33 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia33 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia33 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia33 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia33 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia33 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia33 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia33 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia33 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia33 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia33 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia33 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia33 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia33 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia33 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia33 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia33 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia33 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia33 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - - {"MultiMedia34 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia34 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia34 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia34 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia34 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia34 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia34 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia34 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia34 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia34 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia34 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia34 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia34 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia34 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia34 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia34 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia34 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia34 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia34 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia34 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - - /* connect to INT4_MI2S_DL_HL since same pcm_id */ - {"PRI_TDM_TX_0_UL_HL", NULL, "PRI_TDM_TX_0"}, - {"PRI_TDM_TX_1_UL_HL", NULL, "PRI_TDM_TX_1"}, - {"PRI_TDM_TX_2_UL_HL", NULL, "PRI_TDM_TX_2"}, - {"PRI_TDM_TX_3_UL_HL", NULL, "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0_DL_HL"}, - {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1_DL_HL"}, - {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2_DL_HL"}, - {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3_DL_HL"}, - {"SEC_TDM_TX_0_UL_HL", NULL, "SEC_TDM_TX_0"}, - {"SEC_TDM_TX_1_UL_HL", NULL, "SEC_TDM_TX_1"}, - {"SEC_TDM_TX_2_UL_HL", NULL, "SEC_TDM_TX_2"}, - {"SEC_TDM_TX_3_UL_HL", NULL, "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0_DL_HL"}, - {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1_DL_HL"}, - {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2_DL_HL"}, - {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3_DL_HL"}, - {"SEC_TDM_RX_7", NULL, "SEC_TDM_RX_7_DL_HL"}, - {"TERT_TDM_TX_0_UL_HL", NULL, "TERT_TDM_TX_0"}, - {"TERT_TDM_TX_1_UL_HL", NULL, "TERT_TDM_TX_1"}, - {"TERT_TDM_TX_2_UL_HL", NULL, "TERT_TDM_TX_2"}, - {"TERT_TDM_TX_3_UL_HL", NULL, "TERT_TDM_TX_3"}, - {"TERT_TDM_TX_7_UL_HL", NULL, "TERT_TDM_TX_7"}, - {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0_DL_HL"}, - {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1_DL_HL"}, - {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2_DL_HL"}, - {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3_DL_HL"}, - {"QUAT_TDM_TX_0_UL_HL", NULL, "QUAT_TDM_TX_0"}, - {"QUAT_TDM_TX_1_UL_HL", NULL, "QUAT_TDM_TX_1"}, - {"QUAT_TDM_TX_2_UL_HL", NULL, "QUAT_TDM_TX_2"}, - {"QUAT_TDM_TX_3_UL_HL", NULL, "QUAT_TDM_TX_3"}, - {"QUAT_TDM_TX_7_UL_HL", NULL, "QUAT_TDM_TX_7"}, - {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0_DL_HL"}, - {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1_DL_HL"}, - {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2_DL_HL"}, - {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3_DL_HL"}, - {"QUAT_TDM_RX_7", NULL, "QUAT_TDM_RX_7_DL_HL"}, - {"QUIN_TDM_TX_0_UL_HL", NULL, "QUIN_TDM_TX_0"}, - {"QUIN_TDM_TX_1_UL_HL", NULL, "QUIN_TDM_TX_1"}, - {"QUIN_TDM_TX_2_UL_HL", NULL, "QUIN_TDM_TX_2"}, - {"QUIN_TDM_TX_3_UL_HL", NULL, "QUIN_TDM_TX_3"}, - {"QUIN_TDM_TX_7_UL_HL", NULL, "QUIN_TDM_TX_7"}, - {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0_DL_HL"}, - {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1_DL_HL"}, - {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2_DL_HL"}, - {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3_DL_HL"}, - {"QUIN_TDM_RX_7", NULL, "QUIN_TDM_RX_7_DL_HL"}, {"SEN_TDM_TX_0_UL_HL", NULL, "SEN_TDM_TX_0"}, {"SEN_TDM_TX_1_UL_HL", NULL, "SEN_TDM_TX_1"}, {"SEN_TDM_TX_2_UL_HL", NULL, "SEN_TDM_TX_2"}, @@ -29505,597 +30215,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"HSIF2_TDM_RX_5", NULL, "HSIF2_TDM_RX_5_DL_HL"}, {"HSIF2_TDM_RX_6", NULL, "HSIF2_TDM_RX_6_DL_HL"}, {"HSIF2_TDM_RX_7", NULL, "HSIF2_TDM_RX_7_DL_HL"}, -#ifndef CONFIG_MI2S_DISABLE - {"PRI_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"PRI_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"PRI_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"PRI_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"PRI_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"PRI_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"PRI_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"PRI_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"PRI_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"PRI_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"PRI_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"PRI_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"SEC_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"SEC_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"SEC_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"SEC_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"SEC_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"SEC_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"SEC_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"SEC_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"SEC_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"SEC_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"SEC_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"SEC_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3 Port Mixer"}, - - {"SEC_TDM_RX_7 Port Mixer", "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, - {"SEC_TDM_RX_7", NULL, "SEC_TDM_RX_7 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"TERT_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"TERT_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"TERT_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"TERT_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"TERT_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"TERT_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"TERT_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"TERT_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"TERT_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"TERT_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, -#endif - {"TERT_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"TERT_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"QUAT_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, -#endif - {"QUAT_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"QUAT_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"QUAT_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, -#endif - {"QUAT_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"QUAT_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"QUAT_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, -#endif - {"QUAT_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"QUAT_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"QUAT_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, -#endif - {"QUAT_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"QUAT_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3 Port Mixer"}, - - {"QUAT_TDM_RX_7 Port Mixer", "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, - {"QUAT_TDM_RX_7 Port Mixer", "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}, - {"QUAT_TDM_RX_7", NULL, "QUAT_TDM_RX_7 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"QUIN_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, -#endif - {"QUIN_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"QUIN_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"QUIN_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, -#endif - {"QUIN_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"QUIN_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"QUIN_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, -#endif - {"QUIN_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"QUIN_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2 Port Mixer"}, - -#ifndef CONFIG_MI2S_DISABLE - {"QUIN_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, -#endif - {"QUIN_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, -#ifndef CONFIG_AUXPCM_DISABLE - {"QUIN_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, -#endif - {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3 Port Mixer"}, - - {"QUIN_TDM_RX_7 Port Mixer", "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, - {"QUIN_TDM_RX_7 Port Mixer", "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, - {"QUIN_TDM_RX_7 Port Mixer", "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}, - {"QUIN_TDM_RX_7", NULL, "QUIN_TDM_RX_7 Port Mixer"}, #ifndef CONFIG_MI2S_DISABLE {"SEN_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, @@ -30949,78 +31068,7 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"HSIF2_TDM_RX_7 Port Mixer", "HSIF2_TDM_TX_2", "HSIF2_TDM_TX_2"}, {"HSIF2_TDM_RX_7 Port Mixer", "HSIF2_TDM_TX_3", "HSIF2_TDM_TX_3"}, {"HSIF2_TDM_RX_7", NULL, "HSIF2_TDM_RX_7 Port Mixer"}, - {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_0", "QUAT_TDM_RX_0"}, - {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_1", "QUAT_TDM_RX_1"}, - {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_2", "QUAT_TDM_RX_2"}, - {"AUDIO_REF_EC_UL1 MUX", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"AUDIO_REF_EC_UL1 MUX", "TERT_TDM_RX_2", "TERT_TDM_RX_2"}, - {"AUDIO_REF_EC_UL1 MUX", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"AUDIO_REF_EC_UL1 MUX", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"AUDIO_REF_EC_UL1 MUX", "PRI_TDM_RX_0", "PRI_TDM_RX_0"}, - {"AUDIO_REF_EC_UL1 MUX", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_0", "QUAT_TDM_RX_0"}, - {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_1", "QUAT_TDM_RX_1"}, - {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_2", "QUAT_TDM_RX_2"}, - {"AUDIO_REF_EC_UL10 MUX", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"AUDIO_REF_EC_UL10 MUX", "TERT_TDM_RX_2", "TERT_TDM_RX_2"}, - {"AUDIO_REF_EC_UL10 MUX", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"AUDIO_REF_EC_UL10 MUX", "PRI_TDM_RX_0", "PRI_TDM_RX_0"}, - {"AUDIO_REF_EC_UL10 MUX", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - - {"LSM1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM2 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM2 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM3 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM3 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM4 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM4 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM5 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM5 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM6 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM6 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM7 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM7 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM8 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM8 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - - {"LSM1 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"LSM2 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"LSM3 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"LSM4 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"LSM5 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"LSM6 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"LSM7 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"LSM8 Mixer", "AFE_PCM_TX", "PCM_TX"}, - - /* Backend Enablement */ - {"BE_OUT", NULL, "PRI_TDM_RX_0"}, - {"BE_OUT", NULL, "PRI_TDM_RX_1"}, - {"BE_OUT", NULL, "PRI_TDM_RX_2"}, - {"BE_OUT", NULL, "PRI_TDM_RX_3"}, - {"BE_OUT", NULL, "SEC_TDM_RX_0"}, - {"BE_OUT", NULL, "SEC_TDM_RX_1"}, - {"BE_OUT", NULL, "SEC_TDM_RX_2"}, - {"BE_OUT", NULL, "SEC_TDM_RX_3"}, - {"BE_OUT", NULL, "SEC_TDM_RX_7"}, - {"BE_OUT", NULL, "TERT_TDM_RX_0"}, - {"BE_OUT", NULL, "TERT_TDM_RX_1"}, - {"BE_OUT", NULL, "TERT_TDM_RX_2"}, - {"BE_OUT", NULL, "TERT_TDM_RX_3"}, - {"BE_OUT", NULL, "TERT_TDM_RX_4"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_0"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_1"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_2"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_3"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_7"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_0"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_1"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_2"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_3"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_7"}, {"BE_OUT", NULL, "SEN_TDM_RX_0"}, {"BE_OUT", NULL, "SEN_TDM_RX_1"}, {"BE_OUT", NULL, "SEN_TDM_RX_2"}, @@ -31058,29 +31106,6 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"BE_OUT", NULL, "HSIF2_TDM_RX_6"}, {"BE_OUT", NULL, "HSIF2_TDM_RX_7"}, - {"PRI_TDM_TX_0", NULL, "BE_IN"}, - {"PRI_TDM_TX_1", NULL, "BE_IN"}, - {"PRI_TDM_TX_2", NULL, "BE_IN"}, - {"PRI_TDM_TX_3", NULL, "BE_IN"}, - {"SEC_TDM_TX_0", NULL, "BE_IN"}, - {"SEC_TDM_TX_1", NULL, "BE_IN"}, - {"SEC_TDM_TX_2", NULL, "BE_IN"}, - {"SEC_TDM_TX_3", NULL, "BE_IN"}, - {"TERT_TDM_TX_0", NULL, "BE_IN"}, - {"TERT_TDM_TX_1", NULL, "BE_IN"}, - {"TERT_TDM_TX_2", NULL, "BE_IN"}, - {"TERT_TDM_TX_3", NULL, "BE_IN"}, - {"TERT_TDM_TX_7", NULL, "BE_IN"}, - {"QUAT_TDM_TX_0", NULL, "BE_IN"}, - {"QUAT_TDM_TX_1", NULL, "BE_IN"}, - {"QUAT_TDM_TX_2", NULL, "BE_IN"}, - {"QUAT_TDM_TX_3", NULL, "BE_IN"}, - {"QUAT_TDM_TX_7", NULL, "BE_IN"}, - {"QUIN_TDM_TX_0", NULL, "BE_IN"}, - {"QUIN_TDM_TX_1", NULL, "BE_IN"}, - {"QUIN_TDM_TX_2", NULL, "BE_IN"}, - {"QUIN_TDM_TX_3", NULL, "BE_IN"}, - {"QUIN_TDM_TX_7", NULL, "BE_IN"}, {"SEN_TDM_TX_0", NULL, "BE_IN"}, {"SEN_TDM_TX_1", NULL, "BE_IN"}, {"SEN_TDM_TX_2", NULL, "BE_IN"}, @@ -31118,6 +31143,7 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"HSIF2_TDM_TX_6", NULL, "BE_IN"}, {"HSIF2_TDM_TX_7", NULL, "BE_IN"}, }; + #endif #ifndef CONFIG_MI2S_DISABLE @@ -33167,14 +33193,42 @@ static const struct snd_pcm_ops msm_routing_pcm_ops = { #ifndef CONFIG_TDM_DISABLE static void snd_soc_dapm_new_controls_tdm(struct snd_soc_component *component) { + struct device_node *node = NULL; + char *snd_card_name = NULL; + node = of_find_node_by_path("/soc/qcom,msm-audio-apr/qcom,q6core-audio/sound-adp-star"); + of_property_read_string(node,"compatible",(const char **)&snd_card_name); snd_soc_dapm_new_controls(&component->dapm, msm_qdsp6_widgets_tdm, ARRAY_SIZE(msm_qdsp6_widgets_tdm)); + + + if( !(strstr(snd_card_name, "sa8155") || + strstr(snd_card_name, "sa6155") || + strstr(snd_card_name, "sa8195"))) + { + snd_soc_dapm_new_controls(&component->dapm, + msm_qdsp6_widgets_tdm_gen4, + ARRAY_SIZE(msm_qdsp6_widgets_tdm_gen4)); + } } static void snd_soc_dapm_add_routes_tdm(struct snd_soc_component *component) { + struct device_node *node = NULL; + char *snd_card_name = NULL; + node = of_find_node_by_path("/soc/qcom,msm-audio-apr/qcom,q6core-audio/sound-adp-star"); + of_property_read_string(node,"compatible",(const char **)&snd_card_name); + snd_soc_dapm_add_routes(&component->dapm, intercon_tdm, ARRAY_SIZE(intercon_tdm)); + + if( !(strstr(snd_card_name, "sa8155") || + strstr(snd_card_name, "sa6155") || + strstr(snd_card_name, "sa8195"))) + { + snd_soc_dapm_add_routes(&component->dapm, + intercon_tdm_gen4, + ARRAY_SIZE(intercon_tdm_gen4)); + } } #else static void snd_soc_dapm_new_controls_tdm(struct snd_soc_component *component)