diff --git a/qcom/shima-gdsc.dtsi b/qcom/shima-gdsc.dtsi
new file mode 100644
index 000000000000..ea626abfbe1f
--- /dev/null
+++ b/qcom/shima-gdsc.dtsi
@@ -0,0 +1,192 @@
+&soc {
+	/* GDSCs in GCC */
+	gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
+		compatible = "regulator-fixed";
+		reg = <0x16b004 0x4>;
+		regulator-name = "gcc_pcie_0_gdsc";
+		status = "disabled";
+	};
+
+	gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
+		compatible = "regulator-fixed";
+		reg = <0x18d004 0x4>;
+		regulator-name = "gcc_pcie_1_gdsc";
+		status = "disabled";
+	};
+
+	gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
+		compatible = "regulator-fixed";
+		reg = <0x177004 0x4>;
+		regulator-name = "gcc_ufs_phy_gdsc";
+		status = "disabled";
+	};
+
+	gcc_usb30_prim_gdsc: qcom,gdsc@10f004 {
+		compatible = "regulator-fixed";
+		reg = <0x10f004 0x4>;
+		regulator-name = "gcc_usb30_prim_gdsc";
+		status = "disabled";
+	};
+
+	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c {
+		compatible = "regulator-fixed";
+		reg = <0x17d05c 0x4>;
+		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
+		qcom,gds-timeout = <500>;
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
+		compatible = "regulator-fixed";
+		reg = <0x17d058 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
+		qcom,gds-timeout = <500>;
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
+		compatible = "regulator-fixed";
+		reg = <0x17d054 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
+		qcom,gds-timeout = <500>;
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
+		compatible = "regulator-fixed";
+		reg = <0x17d050 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
+		qcom,gds-timeout = <500>;
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 {
+		compatible = "regulator-fixed";
+		reg = <0x17d060 0x4>;
+		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
+		qcom,gds-timeout = <500>;
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	/* GDSCs in CAMCC */
+	cam_cc_titan_top_gdsc: qcom,gdsc@ad0c120 {
+		compatible = "regulator-fixed";
+		reg = <0xad0c120 0x4>;
+		regulator-name = "cam_cc_titan_top_gdsc";
+		status = "disabled";
+	};
+
+	cam_cc_bps_gdsc: qcom,gdsc@ad07004 {
+		compatible = "regulator-fixed";
+		reg = <0xad07004 0x4>;
+		regulator-name = "cam_cc_bps_gdsc";
+		status = "disabled";
+	};
+
+	cam_cc_ife_0_gdsc: qcom,gdsc@ad0a004 {
+		compatible = "regulator-fixed";
+		reg = <0xad0a004 0x4>;
+		regulator-name = "cam_cc_ife_0_gdsc";
+		status = "disabled";
+	};
+
+	cam_cc_ife_1_gdsc: qcom,gdsc@ad0b004 {
+		compatible = "regulator-fixed";
+		reg = <0xad0b004 0x4>;
+		regulator-name = "cam_cc_ife_1_gdsc";
+		status = "disabled";
+	};
+
+	cam_cc_ife_2_gdsc: qcom,gdsc@ad0b070 {
+		compatible = "regulator-fixed";
+		reg = <0xad0b070 0x4>;
+		regulator-name = "cam_cc_ife_2_gdsc";
+		status = "disabled";
+	};
+
+	cam_cc_ipe_0_gdsc: qcom,gdsc@ad08004 {
+		compatible = "regulator-fixed";
+		reg = <0xad08004 0x4>;
+		regulator-name = "cam_cc_ipe_0_gdsc";
+		status = "disabled";
+	};
+
+	/* GDSCs in DISPCC */
+	disp_cc_mdss_core_gdsc: qcom,gdsc@af03000 {
+		compatible = "regulator-fixed";
+		reg = <0xaf03000 0x4>;
+		regulator-name = "disp_cc_mdss_core_gdsc";
+		proxy-supply = <&disp_cc_mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		status = "disabled";
+	};
+
+	/* GDSCs in GPUCC */
+	gpu_gx_domain_addr: syscon@3d9158c {
+		compatible = "syscon";
+		reg = <0x3d9158c 0x4>;
+	};
+
+	gpu_cx_hw_ctrl: syscon@3d91540 {
+		compatible = "syscon";
+		reg = <0x3d91540 0x4>;
+	};
+
+	gpu_gx_sw_reset: syscon@3d91008 {
+		compatible = "syscon";
+		reg = <0x3d91008 0x4>;
+	};
+
+	gpu_cx_gdsc: qcom,gdsc@3d9106c {
+		compatible = "regulator-fixed";
+		reg = <0x3d9106c 0x4>;
+		regulator-name = "gpu_cx_gdsc";
+		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	gpu_gx_gdsc: qcom,gdsc@3d9100c {
+		compatible = "regulator-fixed";
+		reg = <0x3d9100c 0x4>;
+		regulator-name = "gpu_gx_gdsc";
+		sw-reset = <&gpu_gx_sw_reset>;
+		domain-addr = <&gpu_gx_domain_addr>;
+		qcom,reset-aon-logic;
+		status = "disabled";
+	};
+
+	/* GDSCs in VIDEOCC */
+	video_cc_mvs0_gdsc: qcom,gdsc@abf0d18 {
+		compatible = "regulator-fixed";
+		reg = <0xabf0d18 0x4>;
+		regulator-name = "video_cc_mvs0_gdsc";
+		status = "disabled";
+	};
+
+	video_cc_mvs0c_gdsc: qcom,gdsc@abf0bf8 {
+		compatible = "regulator-fixed";
+		reg = <0xabf0bf8 0x4>;
+		regulator-name = "video_cc_mvs0c_gdsc";
+		status = "disabled";
+	};
+
+	video_cc_mvs1_gdsc: qcom,gdsc@abf0d98 {
+		compatible = "regulator-fixed";
+		reg = <0xabf0d98 0x4>;
+		regulator-name = "video_cc_mvs1_gdsc";
+		status = "disabled";
+	};
+
+	video_cc_mvs1c_gdsc: qcom,gdsc@abf0c98 {
+		compatible = "regulator-fixed";
+		reg = <0xabf0c98 0x4>;
+		regulator-name = "video_cc_mvs1c_gdsc";
+		status = "disabled";
+	};
+};
diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 19cd507fd0bb..5d5edfa959d8 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -1,3 +1,10 @@
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,camcc-shima.h>
+#include <dt-bindings/clock/qcom,dispcc-shima.h>
+#include <dt-bindings/clock/qcom,gcc-shima.h>
+#include <dt-bindings/clock/qcom,gpucc-shima.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,videocc-shima.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -293,7 +300,209 @@
 			status = "disabled";
 		};
 	};
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <38400000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32764>;
+			clock-output-names = "chip_sleep_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	bi_tcxo: bi_tcxo {
+		compatible = "fixed-factor-clock";
+		clock-mult = <1>;
+		clock-div = <2>;
+		clocks = <&xo_board>;
+		#clock-cells = <0>;
+	};
+
+	bi_tcxo_ao: bi_tcxo_ao {
+		compatible = "fixed-factor-clock";
+		clock-mult = <1>;
+		clock-div = <2>;
+		clocks = <&xo_board>;
+		#clock-cells = <0>;
+	};
+
+	aopcc: qcom,aopcc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "aopcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	rpmhcc: qcom,rpmhcc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "rpmhcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gcc: qcom,gcc@100000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	camcc: qcom,camcc@ad00000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "camcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	dispcc: qcom,dispcc@af00000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "dispcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gpucc: qcom,gpucc@3d90000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gpucc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	videocc: qcom,videocc@abf0000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "videocc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
 };
 
 #include "shima-pinctrl.dtsi"
 #include "shima-stub-regulator.dtsi"
+#include "shima-gdsc.dtsi"
+
+&gcc_pcie_0_gdsc {
+	status = "ok";
+};
+
+&gcc_pcie_1_gdsc {
+	status = "ok";
+};
+
+&gcc_ufs_phy_gdsc {
+	status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+	status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
+	status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
+	status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
+	status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu0_gdsc {
+	status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu1_gdsc {
+	status = "ok";
+};
+
+&cam_cc_titan_top_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_bps_gdsc {
+	qcom,support-hw-trigger;
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_ife_0_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_ife_1_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_ife_2_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_ipe_0_gdsc {
+	qcom,support-hw-trigger;
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&disp_cc_mdss_core_gdsc {
+	qcom,support-hw-trigger;
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gpu_cx_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gpu_gx_gdsc {
+	parent-supply = <&VDD_GFX_LEVEL>;
+	vdd_parent-supply = <&VDD_GFX_LEVEL>;
+	status = "ok";
+};
+
+&video_cc_mvs0_gdsc {
+	qcom,support-hw-trigger;
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&video_cc_mvs0c_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&video_cc_mvs1_gdsc {
+	qcom,support-hw-trigger;
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&video_cc_mvs1c_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	vdd_parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+