A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-11 23:24:22 -04:00
Code Issues Projects Releases Packages Wiki Activity

clk: qcom: lahaina: Enable common regulator handle initialization

Browse source 
Enable common regulator handle initialization by adding clk regulator
vote data and clean up clock controllers probe functions to allow
them to move to common clock regulator initialization at one place.

Change-Id: I058982d5e5ed6db7bf856e16b6d39bc0e68f44f3
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
This commit is contained in:
Vivek Aknurwar 2020-05-05 22:24:27 -07:00 • committed by Gerrit - the friendly Code Review server
commit a0bcc432eb
5 changed files with 41 additions and 58 deletions
Download patch file Download diff file Expand all files Collapse all files

27
drivers/clk/qcom/camcc-lahaina.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk.h>
@ -24,8 +24,13 @@
#include "reset.h"
#include "vdd-level.h"
static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NOMINAL + 1, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH + 1, 1, vdd_corner);
static struct clk_vdd_class *cam_cc_lahaina_regulators[] = {
&vdd_mm,
&vdd_mx,
};
enum {
P_BI_TCXO,
@ -2946,6 +2951,8 @@ static const struct qcom_cc_desc cam_cc_lahaina_desc = {
.num_clks = ARRAY_SIZE(cam_cc_lahaina_clocks),
.resets = cam_cc_lahaina_resets,
.num_resets = ARRAY_SIZE(cam_cc_lahaina_resets),
.clk_regulators = cam_cc_lahaina_regulators,
.num_clk_regulators = ARRAY_SIZE(cam_cc_lahaina_regulators),
};
static const struct of_device_id cam_cc_lahaina_match_table[] = {
@ -2968,20 +2975,6 @@ static int cam_cc_lahaina_probe(struct platform_device *pdev)
}
devm_clk_put(&pdev->dev, clk);
vdd_mm.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mm");
if (IS_ERR(vdd_mm.regulator[0])) {
if (PTR_ERR(vdd_mm.regulator[0]) != -EPROBE_DEFER)
dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n");
return PTR_ERR(vdd_mm.regulator[0]);
}
vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
if (IS_ERR(vdd_mx.regulator[0])) {
if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)
dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n");
return PTR_ERR(vdd_mx.regulator[0]);
}
regmap = qcom_cc_map(pdev, &cam_cc_lahaina_desc);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "Failed to map cam CC registers\n");

15
drivers/clk/qcom/dispcc-lahaina.c
View file

@ -24,7 +24,11 @@
#include "reset.h"
#include "vdd-level.h"
static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NOMINAL + 1, 1, vdd_corner);
static struct clk_vdd_class *disp_cc_lahaina_regulators[] = {
&vdd_mm,
};
#define DISP_CC_MISC_CMD 0x8000
@ -1515,6 +1519,8 @@ static const struct qcom_cc_desc disp_cc_lahaina_desc = {
.num_clks = ARRAY_SIZE(disp_cc_lahaina_clocks),
.resets = disp_cc_lahaina_resets,
.num_resets = ARRAY_SIZE(disp_cc_lahaina_resets),
.clk_regulators = disp_cc_lahaina_regulators,
.num_clk_regulators = ARRAY_SIZE(disp_cc_lahaina_regulators),
};
static const struct of_device_id disp_cc_lahaina_match_table[] = {
@ -1529,13 +1535,6 @@ static int disp_cc_lahaina_probe(struct platform_device *pdev)
struct clk *clk;
int ret;
vdd_mm.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mm");
if (IS_ERR(vdd_mm.regulator[0])) {
if (PTR_ERR(vdd_mm.regulator[0]) != -EPROBE_DEFER)
dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n");
return PTR_ERR(vdd_mm.regulator[0]);
}
regmap = qcom_cc_map(pdev, &disp_cc_lahaina_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);

15
drivers/clk/qcom/gcc-lahaina.c
View file

@ -28,7 +28,11 @@
#include "reset.h"
#include "vdd-level.h"
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner);
static struct clk_vdd_class *gcc_lahaina_regulators[] = {
&vdd_cx,
};
enum {
P_BI_TCXO,
@ -4368,6 +4372,8 @@ static const struct qcom_cc_desc gcc_lahaina_desc = {
.num_resets = ARRAY_SIZE(gcc_lahaina_resets),
.clk_hws = gcc_lahaina_hws,
.num_clk_hws = ARRAY_SIZE(gcc_lahaina_hws),
.clk_regulators = gcc_lahaina_regulators,
.num_clk_regulators = ARRAY_SIZE(gcc_lahaina_regulators),
};
static const struct of_device_id gcc_lahaina_match_table[] = {
@ -4381,13 +4387,6 @@ static int gcc_lahaina_probe(struct platform_device *pdev)
struct regmap *regmap;
int ret;
vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
if (IS_ERR(vdd_cx.regulator[0])) {
if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
return PTR_ERR(vdd_cx.regulator[0]);
}
regmap = qcom_cc_map(pdev, &gcc_lahaina_desc);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "Failed to map gcc registers\n");

15
drivers/clk/qcom/gpucc-lahaina.c
View file

@ -24,7 +24,11 @@
#include "reset.h"
#include "vdd-level.h"
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NOMINAL + 1, 1, vdd_corner);
static struct clk_vdd_class *gpu_cc_lahaina_regulators[] = {
&vdd_mx,
};
enum {
P_BI_TCXO,
@ -596,6 +600,8 @@ static const struct qcom_cc_desc gpu_cc_lahaina_desc = {
.num_clks = ARRAY_SIZE(gpu_cc_lahaina_clocks),
.resets = gpu_cc_lahaina_resets,
.num_resets = ARRAY_SIZE(gpu_cc_lahaina_resets),
.clk_regulators = gpu_cc_lahaina_regulators,
.num_clk_regulators = ARRAY_SIZE(gpu_cc_lahaina_regulators),
};
static const struct of_device_id gpu_cc_lahaina_match_table[] = {
@ -609,13 +615,6 @@ static int gpu_cc_lahaina_probe(struct platform_device *pdev)
struct regmap *regmap;
int ret;
vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
if (IS_ERR(vdd_mx.regulator[0])) {
if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)
dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n");
return PTR_ERR(vdd_mx.regulator[0]);
}
regmap = qcom_cc_map(pdev, &gpu_cc_lahaina_desc);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "Failed to map gpu cc registers\n");

27
drivers/clk/qcom/videocc-lahaina.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk.h>
@ -24,8 +24,13 @@
#include "reset.h"
#include "vdd-level.h"
static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NOMINAL + 1, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NOMINAL + 1, 1, vdd_corner);
static struct clk_vdd_class *video_cc_lahaina_regulators[] = {
&vdd_mm,
&vdd_mx
};
enum {
P_BI_TCXO,
@ -550,6 +555,8 @@ static const struct qcom_cc_desc video_cc_lahaina_desc = {
.num_clks = ARRAY_SIZE(video_cc_lahaina_clocks),
.resets = video_cc_lahaina_resets,
.num_resets = ARRAY_SIZE(video_cc_lahaina_resets),
.clk_regulators = video_cc_lahaina_regulators,
.num_clk_regulators = ARRAY_SIZE(video_cc_lahaina_regulators),
};
static const struct of_device_id video_cc_lahaina_match_table[] = {
@ -564,20 +571,6 @@ static int video_cc_lahaina_probe(struct platform_device *pdev)
struct clk *clk;
int ret;
vdd_mm.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mm");
if (IS_ERR(vdd_mm.regulator[0])) {
if (PTR_ERR(vdd_mm.regulator[0]) != -EPROBE_DEFER)
dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n");
return PTR_ERR(vdd_mm.regulator[0]);
}
vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
if (IS_ERR(vdd_mx.regulator[0])) {
if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)
dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n");
return PTR_ERR(vdd_mx.regulator[0]);
}
regmap = qcom_cc_map(pdev, &video_cc_lahaina_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);