From a13e8cd0f913a48f83504bf77fdd16989655bbd4 Mon Sep 17 00:00:00 2001
From: Saurabh Sahu <sausah@qti.qualcomm.com>
Date: Fri, 19 Mar 2021 18:42:09 +0530
Subject: [PATCH] ARM: dts: msm: Add DISPCC/DEBUGCC clock node for MONACO

Add DISPCC clock nodes which is required for clocks client to request,
so add support for the same. Add debug clock controller to support
measure functionality for all clock controllers. Also add the disp GDSCs
required by clients for MONACO.

Change-Id: Ibed0e45fef8b88a972c2b154c43f1b38ce62d388
---
 qcom/monaco-gdsc.dtsi |  2 +-
 qcom/monaco.dtsi      | 30 ++++++++++++++++++++++++++++--
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/qcom/monaco-gdsc.dtsi b/qcom/monaco-gdsc.dtsi
index dfa39a8cdaa4..88829cb6e9fa 100644
--- a/qcom/monaco-gdsc.dtsi
+++ b/qcom/monaco-gdsc.dtsi
@@ -46,7 +46,7 @@
 
 	/* GDSCs in DISPCC */
 	mdss_core_gdsc: qcom,gdsc@5f03000 {
-		compatible = "regulator-fixed";
+		compatible = "qcom,gdsc";
 		reg = <0x5f03000 0x4>;
 		regulator-name = "mdss_core_gdsc";
 		proxy-supply = <&mdss_core_gdsc>;
diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
index b753f2c41340..3e9883ccbcad 100644
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -698,8 +698,14 @@
 	};
 
 	dispcc: clock-controller@5f00000 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "dispcc_clocks";
+		compatible = "qcom,monaco-dispcc", "syscon";
+		reg = <0x05f00000 0x20000>;
+		reg-names = "cc_base";
+		clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main",
+			"sleep_clk";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+			 <&gcc GPLL0>, <&sleep_clk>;
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -711,6 +717,26 @@
 		#reset-cells = <1>;
 	};
 
+	mccc_debug: syscon@447d200 {
+		compatible = "syscon";
+	};
+
+	apsscc_debug: syscon@f11101c {
+		compatible = "syscon";
+	};
+
+	debugcc: clock-controller@0 {
+		compatible = "qcom,monaco-debugcc";
+		qcom,gcc = <&gcc>;
+		qcom,dispcc = <&dispcc>;
+		qcom,gpucc = <&gpucc>;
+		qcom,mccc = <&mccc_debug>;
+		qcom,apsscc = <&apsscc_debug>;
+		clock-names = "xo_clk_src";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+		#clock-cells = <1>;
+	};
+
 	cpufreq_hw: qcom,cpufreq-hw {
 		compatible = "qcom,cpufreq-hw";
 		reg = <0xf521000 0x1400>;