diff --git a/qcom/holi-rumi.dtsi b/qcom/holi-rumi.dtsi index ca46c5888ec5..2f9dce529bb8 100644 --- a/qcom/holi-rumi.dtsi +++ b/qcom/holi-rumi.dtsi @@ -37,6 +37,7 @@ }; &usb0 { + dpdm-supply = <&usb_nop_phy>; dwc3@4e00000 { usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; maximum-speed = "high-speed"; diff --git a/qcom/holi-usb.dtsi b/qcom/holi-usb.dtsi index 1d719c32e377..c74358d082c0 100644 --- a/qcom/holi-usb.dtsi +++ b/qcom/holi-usb.dtsi @@ -1,4 +1,5 @@ #include +#include &soc { /* Primary USB port related controller */ @@ -29,9 +30,12 @@ reset-names = "core_reset"; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + qcom,usb-charger; qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ @@ -47,22 +51,260 @@ reg = <0x4e00000 0xcd00>; interrupt-parent = <&intc>; interrupts = ; + usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>; tx-fifo-resize; linux,sysdev_is_parent; snps,disable-clk-gating; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; + snps,hird-threshold = /bits/ 8 <0x0>; snps,usb3_lpm_capable; - usb-core-id = <0>; maximum-speed = "super-speed"; dr_mode = "otg"; }; }; + /* Primary USB port related QUSB2 PHY */ + qusb_phy0: qusb@162b000 { + compatible = "qcom,qusb2phy-v2"; + reg = <0x0162b000 0x400>, + <0x1b40268 0x4>, + <0x0162f014 0x4>; + reg-names = "qusb_phy_base", "efuse_addr", + "refgen_north_bg_reg_addr"; + + qcom,efuse-bit-pos = <25>; + qcom,efuse-num-bits = <3>; + vdd-supply = <&L18A>; + vdda18-supply = <&L2A>; + vdda33-supply = <&L3A>; + refgen-supply = <&L22A>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,qusb-phy-reg-offset = + <0x240 /* QUSB2PHY_PORT_TUNE1 */ + 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */ + 0x210 /* QUSB2PHY_PWR_CTRL1 */ + 0x230 /* QUSB2PHY_INTR_CTRL */ + 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */ + 0x254 /* QUSB2PHY_TEST1 */ + 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x27c /* QUSB2PHY_DEBUG_CTRL1 */ + 0x280 /* QUSB2PHY_DEBUG_CTRL2 */ + 0x284 /* QUSB2PHY_DEBUG_CTRL3 */ + 0x288 /* QUSB2PHY_DEBUG_CTRL4 */ + 0x2a0>; /* QUSB2PHY_STAT5 */ + + qcom,qusb-phy-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x45 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x30 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ + + qcom,qusb-phy-host-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x45 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x30 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ + + phy_type= "utmi"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* Primary USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@1630000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x1630000 0x3000>; + reg-names = "qmp_phy_base"; + vdd-supply = <&L16A>; + qcom,vdd-voltage-level = <0 880000 880000>; + core-supply = <&L22A>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + }; + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x0af 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; };