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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 06:03:36 -04:00
Merge "dt-bindings: clock: Add support for clock ids for SDXNIGHTJAR"
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qctecmdr
Gerrit - the friendly Code Review server
commit
a15fa3b052
2 changed files with 174 additions and 2 deletions
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@ -878,6 +878,69 @@ static const struct rpm_smd_clk_desc rpm_clk_holi = {
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.num_clks = ARRAY_SIZE(holi_clks),
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};
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DEFINE_CLK_SMD_RPM(sdxnightjar, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
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DEFINE_CLK_SMD_RPM(sdxnightjar, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
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/* SMD_XO_BUFFER */
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DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, ln_bb_clk, ln_bb_clk_a,
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QCOM_SMD_RPM_CLK_BUF_A, 8);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, div_clk1, div_clk1_a,
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QCOM_SMD_RPM_CLK_BUF_A, 0xb);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, rf_clk1, rf_clk1_a,
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QCOM_SMD_RPM_CLK_BUF_A, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, rf_clk2, rf_clk2_a,
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QCOM_SMD_RPM_CLK_BUF_A, 5);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, rf_clk3, rf_clk3_a,
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QCOM_SMD_RPM_CLK_BUF_A, 6);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdxnightjar, rf_clk1_pin, rf_clk1_a_pin,
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QCOM_SMD_RPM_CLK_BUF_A, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdxnightjar, rf_clk2_pin, rf_clk2_a_pin,
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QCOM_SMD_RPM_CLK_BUF_A, 5);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdxnightjar, rf_clk3_pin, rf_clk3_a_pin,
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QCOM_SMD_RPM_CLK_BUF_A, 6);
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/* SDXNIGHTJAR */
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static struct clk_hw *sdxnightjar_clks[] = {
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[RPM_SMD_XO_CLK_SRC] = &holi_bi_tcxo.hw,
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[RPM_SMD_XO_A_CLK_SRC] = &holi_bi_tcxo_ao.hw,
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[RPM_SMD_SNOC_CLK] = &sdxnightjar_snoc_clk.hw,
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[RPM_SMD_SNOC_A_CLK] = &sdxnightjar_snoc_a_clk.hw,
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[RPM_SMD_BIMC_CLK] = &holi_bimc_clk.hw,
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[RPM_SMD_BIMC_A_CLK] = &holi_bimc_a_clk.hw,
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[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk.hw,
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[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk.hw,
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[RPM_SMD_IPA_CLK] = &holi_ipa_clk.hw,
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[RPM_SMD_IPA_A_CLK] = &holi_ipa_a_clk.hw,
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[RPM_SMD_CE1_CLK] = &holi_ce1_clk.hw,
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[RPM_SMD_CE1_A_CLK] = &holi_ce1_a_clk.hw,
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[RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk.hw,
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[RPM_SMD_QPIC_A_CLK] = &qcs404_qpic_a_clk.hw,
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[RPM_SMD_PCNOC_CLK] = &sdxnightjar_pcnoc_clk.hw,
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[RPM_SMD_PCNOC_A_CLK] = &sdxnightjar_pcnoc_a_clk.hw,
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[RPM_SMD_LN_BB_CLK] = &sdxnightjar_ln_bb_clk.hw,
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[RPM_SMD_LN_BB_CLK_A] = &sdxnightjar_ln_bb_clk_a.hw,
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[RPM_SMD_DIV_CLK1] = &sdxnightjar_div_clk1.hw,
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[RPM_SMD_DIV_A_CLK1] = &sdxnightjar_div_clk1_a.hw,
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[RPM_SMD_RF_CLK1] = &sdxnightjar_rf_clk1.hw,
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[RPM_SMD_RF_CLK1_A] = &sdxnightjar_rf_clk1_a.hw,
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[RPM_SMD_RF_CLK2] = &sdxnightjar_rf_clk2.hw,
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[RPM_SMD_RF_CLK2_A] = &sdxnightjar_rf_clk2_a.hw,
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[RPM_SMD_RF_CLK3] = &sdxnightjar_rf_clk3.hw,
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[RPM_SMD_RF_CLK3_A] = &sdxnightjar_rf_clk3_a.hw,
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[RPM_SMD_RF_CLK1_PIN] = &sdxnightjar_rf_clk1_pin.hw,
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[RPM_SMD_RF_CLK1_A_PIN] = &sdxnightjar_rf_clk1_a_pin.hw,
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[RPM_SMD_RF_CLK2_PIN] = &sdxnightjar_rf_clk2_pin.hw,
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[RPM_SMD_RF_CLK2_A_PIN] = &sdxnightjar_rf_clk2_a_pin.hw,
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[RPM_SMD_RF_CLK3_PIN] = &sdxnightjar_rf_clk3_pin.hw,
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[RPM_SMD_RF_CLK3_A_PIN] = &sdxnightjar_rf_clk3_a_pin.hw,
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};
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static const struct rpm_smd_clk_desc rpm_clk_sdxnightjar = {
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.clks = sdxnightjar_clks,
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.num_clks = ARRAY_SIZE(sdxnightjar_clks),
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};
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static const struct of_device_id rpm_smd_clk_match_table[] = {
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{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
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{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
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@ -885,6 +948,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
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{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
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{ .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
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{ .compatible = "qcom,rpmcc-holi", .data = &rpm_clk_holi},
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{ .compatible = "qcom,rpmcc-sdxnightjar", .data = &rpm_clk_sdxnightjar},
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{ }
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};
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MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
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@ -943,7 +1007,7 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
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{
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struct clk_hw **hw_clks;
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const struct rpm_smd_clk_desc *desc;
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int ret, i, is_holi, hw_clk_handoff = false;
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int ret, i, is_holi, hw_clk_handoff = false, is_sdxnightjar;
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desc = of_device_get_match_data(&pdev->dev);
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if (!desc)
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@ -951,7 +1015,9 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
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is_holi = of_device_is_compatible(pdev->dev.of_node,
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"qcom,rpmcc-holi");
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if (is_holi) {
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is_sdxnightjar = of_device_is_compatible(pdev->dev.of_node,
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"qcom,rpmcc-sdxnightjar");
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if (is_holi || is_sdxnightjar) {
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ret = clk_vote_bimc(&holi_bimc_clk.hw, INT_MAX);
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if (ret < 0)
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return ret;
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@ -1011,6 +1077,22 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
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clk_set_rate(holi_snoc_a_clk.hw.clk, 19200000);
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}
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if (is_sdxnightjar) {
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/*
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* Keep an active vote on CXO in case no other driver
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* votes for it.
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*/
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clk_prepare_enable(holi_bi_tcxo_ao.hw.clk);
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/* Hold an active set vote for the pcnoc_keepalive_a_clk */
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clk_prepare_enable(sdxnightjar_pcnoc_a_clk.hw.clk);
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clk_set_rate(sdxnightjar_pcnoc_a_clk.hw.clk, 19200000);
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/* Hold an active set vote for the snoc_keepalive_a_clk */
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clk_prepare_enable(sdxnightjar_snoc_a_clk.hw.clk);
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clk_set_rate(sdxnightjar_snoc_a_clk.hw.clk, 19200000);
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}
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if (of_property_read_bool(pdev->dev.of_node, "qcom,bimc-log-stop"))
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atomic_notifier_chain_register(&panic_notifier_list,
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&smd_rpm_clk_panic_notifier);
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90
include/dt-bindings/clock/qcom,gcc-sdxnightjar.h
Normal file
90
include/dt-bindings/clock/qcom,gcc-sdxnightjar.h
Normal file
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@ -0,0 +1,90 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDXNIGHTJAR_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SDXNIGHTJAR_H
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/* GCC clocks */
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#define GPLL0 0
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#define GPLL0_AO 1
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#define GPLL0_OUT_MAIN_DIV2 2
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
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#define BLSP1_UART1_APPS_CLK_SRC 11
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#define BLSP1_UART2_APPS_CLK_SRC 12
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#define BLSP1_UART3_APPS_CLK_SRC 13
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#define BLSP1_UART4_APPS_CLK_SRC 14
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#define GCC_APSS_TCU_CLK 15
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#define GCC_BLSP1_AHB_CLK 16
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 17
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 18
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 19
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 20
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 21
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 22
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 23
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 24
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#define GCC_BLSP1_SLEEP_CLK 25
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#define GCC_BLSP1_UART1_APPS_CLK 26
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#define GCC_BLSP1_UART2_APPS_CLK 27
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#define GCC_BLSP1_UART3_APPS_CLK 28
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#define GCC_BLSP1_UART4_APPS_CLK 29
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#define GCC_BOOT_ROM_AHB_CLK 30
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#define GCC_DCC_CLK 31
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#define GCC_GP1_CLK 32
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#define GCC_GP2_CLK 33
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#define GCC_GP3_CLK 34
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#define GCC_MSS_GPLL0_CLK_SRC 35
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#define GCC_PCIE_AXI_CLK 36
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#define GCC_PCIE_AXI_MSTR_CLK 37
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#define GCC_PCIE_AXI_TBU_CLK 38
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#define GCC_PCIE_CFG_AHB_CLK 39
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#define GCC_PCIE_REF_CLK 40
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#define GCC_PCIE_PIPE_CLK 41
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#define GCC_PCIE_SLEEP_CLK 42
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#define GCC_PDM2_CLK 43
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#define GCC_PDM_AHB_CLK 44
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#define GCC_PDM_XO4_CLK 45
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#define GCC_PRNG_AHB_CLK 46
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#define GCC_QUSB_REF_CLK 47
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#define GCC_SDCC1_AHB_CLK 48
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#define GCC_SDCC1_APPS_CLK 49
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#define GCC_SMMU_CFG_CLK 50
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#define GCC_SYS_NOC_USB3_AXI_CLK 51
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#define GCC_USB30_MASTER_CLK 52
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#define GCC_USB30_MOCK_UTMI_CLK 53
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#define GCC_USB30_SLEEP_CLK 54
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#define GCC_USB3_AUX_CLK 55
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#define GCC_USB3_AXI_TBU_CLK 56
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#define GCC_USB3_PIPE_CLK 57
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#define GCC_USB_PHY_CFG_AHB_CLK 58
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#define GCC_USB_SS_REF_CLK 59
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#define GCC_XO_DIV4_CLK 60
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#define GP1_CLK_SRC 61
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#define GP2_CLK_SRC 62
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#define GP3_CLK_SRC 63
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#define PCIE_AUX_CLK_SRC 64
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#define PDM2_CLK_SRC 65
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#define SDCC1_APPS_CLK_SRC 66
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#define USB30_MASTER_CLK_SRC 67
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#define USB30_MOCK_UTMI_CLK_SRC 68
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#define USB3_AUX_CLK_SRC 69
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#define APSS_AHB_CLK_SRC 70
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/* GCC resets */
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#define GCC_PCIEPHY_PHY_BCR 0
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#define GCC_PCIE_PHY_BCR 1
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#define GCC_USB_30_BCR 2
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#define GCC_USB3_PHY_BCR 3
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#define GCC_USB3PHY_PHY_BCR 4
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#define GCC_QUSB2A_PHY_BCR 5
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#endif
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