From 0070266e70828ff06024e8f78a3e2546e21441b7 Mon Sep 17 00:00:00 2001 From: Vipin Deep Kaur Date: Tue, 17 Nov 2020 12:22:35 +0530 Subject: [PATCH] spi: spi-msm-geni: Clear the RX fifo if FIFO has data after timeout Propagate a change from 4.19 to 5.4 for SPI. 'commit 556e7c13ceaa ("spi: spi-msm-geni: Clear the RX fifo if FIFO has data after timeout")'. Change-Id: Ica785f7b3cd3a9f9df6d173413ce136c2a018312 Signed-off-by: Vipin Deep Kaur --- drivers/spi/spi-msm-geni.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/spi/spi-msm-geni.c b/drivers/spi/spi-msm-geni.c index 68ab4e5677cc..ff812c7cb1ee 100644 --- a/drivers/spi/spi-msm-geni.c +++ b/drivers/spi/spi-msm-geni.c @@ -1384,9 +1384,21 @@ static void handle_fifo_timeout(struct spi_geni_master *mas, struct spi_transfer *xfer) { unsigned long timeout; + u32 rx_fifo_status; + int rx_wc, i; geni_se_dump_dbg_regs(&mas->spi_rsc, mas->base, mas->ipc); reinit_completion(&mas->xfer_done); + + /* Dummy read the rx fifo for any spurious data*/ + if (xfer->rx_buf) { + rx_fifo_status = geni_read_reg(mas->base, + SE_GENI_RX_FIFO_STATUS); + rx_wc = (rx_fifo_status & RX_FIFO_WC_MSK); + for (i = 0; i < rx_wc; i++) + geni_read_reg(mas->base, SE_GENI_RX_FIFOn); + } + geni_cancel_m_cmd(mas->base); if (mas->cur_xfer_mode == FIFO_MODE) geni_write_reg(0, mas->base, SE_GENI_TX_WATERMARK_REG);