From a1bcd20b8053784c807f326cb673062032b31d2e Mon Sep 17 00:00:00 2001 From: Manuel Gomez Date: Tue, 14 Sep 2021 13:24:57 -0700 Subject: [PATCH] ARM: dts: msm: WoL IRQ support for AQR and Napa PHYs Add interrupt properties to configure the WoL interrupt lines that are connected to GPIO103 and GPIO81 on SDX65 from AQR PHY and Napa PHY, respectively. Change-Id: I8a2ce294b094c10ab93f1b21723549faff8f8c3a --- qcom/sdxlemur-mtp-cpe.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 266d6df33c5c..3daca4e6d64c 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -146,6 +146,9 @@ qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth0>; + interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>; @@ -171,6 +174,9 @@ qcom,ioss = <&ioss>; qcom,ioss_interfaces = <&ioss_qps615_eth1>; + interrupts-extended = <&tlmm 81 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wol_irq"; + /* ipa shares this group */ qcom,iommu-group = <&ipa_eth_group1>;