diff --git a/qcom/lahaina-rumi.dtsi b/qcom/lahaina-rumi.dtsi
index 0729aabfcd3a..6ab1732d13b5 100644
--- a/qcom/lahaina-rumi.dtsi
+++ b/qcom/lahaina-rumi.dtsi
@@ -30,3 +30,53 @@
 
 	status = "ok";
 };
+
+&soc {
+	usb_emu_phy_0: usb_emu_phy@a720000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0x0a720000 0x9500>;
+
+		qcom,emu-init-seq = <0xffff 0x4
+				     0xfff0 0x4
+				     0x100000 0x20
+				     0x0 0x20
+				     0x101f0 0x20
+				     0x100000 0x3c
+				     0x0 0x3c
+				     0x10060 0x3c
+				     0x0 0x4>;
+	};
+
+	usb_emu_phy_1: usb_emu_phy@a920000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0x0a920000 0x9500>;
+
+		qcom,emu-init-seq = <0xffff 0x4
+				     0xfff0 0x4
+				     0x100000 0x20
+				     0x0 0x20
+				     0x101f0 0x20
+				     0x100000 0x3c
+				     0x0 0x3c
+				     0x10060 0x3c
+				     0x0 0x4>;
+	};
+};
+
+&usb0 {
+	/delete-property/ extcon;
+	dwc3@a600000 {
+		usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
+		maximum-speed = "high-speed";
+		dr_mode = "peripheral";
+	};
+};
+
+&usb1 {
+	/delete-property/ extcon;
+	dwc3@a800000 {
+		usb-phy = <&usb_emu_phy_1>, <&usb_nop_phy>;
+		maximum-speed = "high-speed";
+		dr_mode = "peripheral";
+	};
+};
diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi
new file mode 100644
index 000000000000..8214d5cfecd9
--- /dev/null
+++ b/qcom/lahaina-usb.dtsi
@@ -0,0 +1,91 @@
+&soc {
+	usb0: ssusb@a6f8800 {
+		compatible = "qcom,dwc3";
+		reg = <0xa6f8800 0x400>;
+		reg-names = "core_base";
+
+		iommus = <&apps_smmu 0x0 0x0>;
+		qcom,iommu-dma = "atomic";
+		qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		dma-ranges;
+
+		clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0xa600000 0xcd00>;
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			linux,sysdev_is_parent;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x10>;
+			snps,ssp-u3-u0-quirk;
+			snps,usb3-u1u2-disable;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_enblslpm_quirk;
+			usb-core-id = <0>;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "drd";
+		};
+	};
+
+	usb1: ssusb@a8f8800 {
+		compatible = "qcom,dwc3";
+		reg = <0xa8f8800 0x400>;
+		reg-names = "core_base";
+
+		iommus = <&apps_smmu 0x20 0x0>;
+		qcom,iommu-dma = "atomic";
+		qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		dma-ranges;
+
+		clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>,
+			<&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+			<&clock_gcc GCC_USB30_SEC_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&clock_gcc GCC_USB30_SEC_BCR>;
+		reset-names = "core_reset";
+
+		dwc3@a800000 {
+			compatible = "snps,dwc3";
+			reg = <0xa800000 0xcd00>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			linux,sysdev_is_parent;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x10>;
+			snps,ssp-u3-u0-quirk;
+			snps,usb3-u1u2-disable;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_enblslpm_quirk;
+			usb-core-id = <0>;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "drd";
+		};
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+};
diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index 3cf17c7fe7b3..d7d91fb6fa0e 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -671,3 +671,4 @@
 
 #include "lahaina-pinctrl.dtsi"
 #include "msm-arm-smmu-lahaina.dtsi"
+#include "lahaina-usb.dtsi"