mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 05:39:54 -04:00
Merge "clk: qcom: clk-debug: Unflatten mux tree"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
a1f29ec6d7
2 changed files with 199 additions and 172 deletions
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@ -10,6 +10,7 @@
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/bitops.h>
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#include <linux/mfd/syscon.h>
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#include "clk-regmap.h"
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#include "clk-debug.h"
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@ -82,9 +83,9 @@ static unsigned long clk_debug_mux_measure_rate(struct clk_hw *hw)
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spin_lock_irqsave(&clk_reg_lock, flags);
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/* Enable CXO/4 and RINGOSC branch. */
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regmap_read(meas->regmap[GCC], data->xo_div4_cbcr, &gcc_xo4_reg);
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regmap_read(meas->regmap, data->xo_div4_cbcr, &gcc_xo4_reg);
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gcc_xo4_reg |= BIT(0);
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regmap_write(meas->regmap[GCC], data->xo_div4_cbcr, gcc_xo4_reg);
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regmap_write(meas->regmap, data->xo_div4_cbcr, gcc_xo4_reg);
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/*
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* The ring oscillator counter will not reset if the measured clock
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@ -94,15 +95,15 @@ static unsigned long clk_debug_mux_measure_rate(struct clk_hw *hw)
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*/
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/* Run a short measurement. (~1 ms) */
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raw_count_short = run_measurement(SAMPLE_TICKS_1_MS, meas->regmap[GCC],
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raw_count_short = run_measurement(SAMPLE_TICKS_1_MS, meas->regmap,
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data->ctl_reg, data->status_reg);
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/* Run a full measurement. (~14 ms) */
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raw_count_full = run_measurement(SAMPLE_TICKS_14_MS, meas->regmap[GCC],
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raw_count_full = run_measurement(SAMPLE_TICKS_14_MS, meas->regmap,
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data->ctl_reg, data->status_reg);
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gcc_xo4_reg &= ~BIT(0);
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regmap_write(meas->regmap[GCC], data->xo_div4_cbcr, gcc_xo4_reg);
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regmap_write(meas->regmap, data->xo_div4_cbcr, gcc_xo4_reg);
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/* Return 0 if the clock is off. */
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if (raw_count_full == raw_count_short)
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@ -121,73 +122,63 @@ static unsigned long clk_debug_mux_measure_rate(struct clk_hw *hw)
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return ret;
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}
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static int clk_find_and_set_parent(struct clk_hw *mux, struct clk_hw *clk)
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{
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int i;
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if (!clk || !mux || !(mux->init->flags & CLK_IS_MEASURE))
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return -EINVAL;
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if (!clk_set_parent(mux->clk, clk->clk))
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return 0;
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for (i = 0; i < clk_hw_get_num_parents(mux); i++) {
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struct clk_hw *parent = clk_hw_get_parent_by_index(mux, i);
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if (!clk_find_and_set_parent(parent, clk))
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return clk_set_parent(mux->clk, parent->clk);
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}
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return -EINVAL;
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}
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static u8 clk_debug_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_debug_mux *meas = to_clk_measure(hw);
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int i, num_parents = clk_hw_get_num_parents(hw);
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struct clk_hw *hw_clk = clk_hw_get_parent(hw);
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if (!hw_clk)
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return 0;
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for (i = 0; i < num_parents; i++) {
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if (!strcmp(meas->parent[i].parents,
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if (!strcmp(hw->init->parent_names[i],
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clk_hw_get_name(hw_clk))) {
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pr_debug("%s: clock parent - %s, index %d\n", __func__,
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meas->parent[i].parents, i);
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hw->init->parent_names[i], i);
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return i;
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}
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}
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return 0;
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}
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static int clk_debug_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_debug_mux *meas = to_clk_measure(hw);
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u32 regval = 0;
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int dbg_cc = 0;
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struct clk_debug_mux *mux = to_clk_measure(hw);
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int ret;
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dbg_cc = meas->parent[index].dbg_cc;
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if (!mux->mux_sels)
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return 0;
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if (dbg_cc != GCC) {
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/* Update the recursive debug mux */
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regmap_read(meas->regmap[dbg_cc],
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meas->parent[index].mux_offset, ®val);
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regval &= ~(meas->parent[index].mux_sel_mask <<
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meas->parent[index].mux_sel_shift);
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regval |= (meas->parent[index].dbg_cc_mux_sel &
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meas->parent[index].mux_sel_mask) <<
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meas->parent[index].mux_sel_shift;
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regmap_write(meas->regmap[dbg_cc],
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meas->parent[index].mux_offset, regval);
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/* Update the debug sel for mux */
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ret = regmap_update_bits(mux->regmap, mux->debug_offset,
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mux->src_sel_mask,
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mux->mux_sels[index] << mux->src_sel_shift);
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if (ret)
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return ret;
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regmap_read(meas->regmap[dbg_cc],
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meas->parent[index].post_div_offset, ®val);
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regval &= ~(meas->parent[index].post_div_mask <<
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meas->parent[index].post_div_shift);
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regval |= ((meas->parent[index].post_div_val - 1) &
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meas->parent[index].post_div_mask) <<
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meas->parent[index].post_div_shift;
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regmap_write(meas->regmap[dbg_cc],
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meas->parent[index].post_div_offset, regval);
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}
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/* Update the debug sel for GCC */
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regmap_read(meas->regmap[GCC], meas->debug_offset, ®val);
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regval &= ~(meas->src_sel_mask << meas->src_sel_shift);
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regval |= (meas->parent[index].prim_mux_sel & meas->src_sel_mask) <<
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meas->src_sel_shift;
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regmap_write(meas->regmap[GCC], meas->debug_offset, regval);
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/* Set the GCC mux's post divider bits */
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regmap_read(meas->regmap[GCC], meas->post_div_offset, ®val);
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regval &= ~(meas->post_div_mask << meas->post_div_shift);
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regval |= ((meas->parent[index].prim_mux_div_val - 1) &
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meas->post_div_mask) << meas->post_div_shift;
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regmap_write(meas->regmap[GCC], meas->post_div_offset, regval);
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return 0;
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/* Set the mux's post divider bits */
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return regmap_update_bits(mux->regmap, mux->post_div_offset,
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mux->post_div_mask,
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(mux->post_div_val - 1) << mux->post_div_shift);
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}
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const struct clk_ops clk_debug_mux_ops = {
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@ -196,90 +187,83 @@ const struct clk_ops clk_debug_mux_ops = {
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};
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EXPORT_SYMBOL(clk_debug_mux_ops);
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static void enable_debug_clks(struct clk_debug_mux *meas, u8 index)
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static void enable_debug_clks(struct clk_hw *mux)
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{
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int dbg_cc = meas->parent[index].dbg_cc;
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struct clk_debug_mux *meas = to_clk_measure(mux);
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struct clk_hw *parent;
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if (!mux || !(mux->init->flags & CLK_IS_MEASURE))
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return;
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parent = clk_hw_get_parent(mux);
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enable_debug_clks(parent);
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meas->en_mask = meas->en_mask ? meas->en_mask : CBCR_ENA;
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if (dbg_cc != GCC) {
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/* Not all recursive muxes have a DEBUG clock. */
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if (meas->parent[index].cbcr_offset != U32_MAX)
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regmap_update_bits(meas->regmap[dbg_cc],
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meas->parent[index].cbcr_offset,
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meas->en_mask, meas->en_mask);
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}
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/* Turn on the GCC_DEBUG_CBCR */
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regmap_update_bits(meas->regmap[GCC], meas->cbcr_offset,
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meas->en_mask, meas->en_mask);
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/* Not all muxes have a DEBUG clock. */
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if (meas->cbcr_offset != U32_MAX)
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regmap_update_bits(meas->regmap, meas->cbcr_offset,
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meas->en_mask, meas->en_mask);
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}
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static void disable_debug_clks(struct clk_debug_mux *meas, u8 index)
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static void disable_debug_clks(struct clk_hw *mux)
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{
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int dbg_cc = meas->parent[index].dbg_cc;
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struct clk_debug_mux *meas = to_clk_measure(mux);
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struct clk_hw *parent;
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if (!mux || !(mux->init->flags & CLK_IS_MEASURE))
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return;
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meas->en_mask = meas->en_mask ? meas->en_mask : CBCR_ENA;
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/* Turn off the GCC_DEBUG_CBCR */
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regmap_update_bits(meas->regmap[GCC], meas->cbcr_offset,
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if (meas->cbcr_offset != U32_MAX)
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regmap_update_bits(meas->regmap, meas->cbcr_offset,
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meas->en_mask, 0);
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if (dbg_cc != GCC) {
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if (meas->parent[index].cbcr_offset != U32_MAX)
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regmap_update_bits(meas->regmap[dbg_cc],
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meas->parent[index].cbcr_offset,
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meas->en_mask, 0);
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parent = clk_hw_get_parent(mux);
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disable_debug_clks(parent);
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}
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static u32 get_mux_divs(struct clk_hw *mux)
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{
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struct clk_debug_mux *meas = to_clk_measure(mux);
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struct clk_hw *parent;
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u32 div_val;
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if (!mux || !(mux->init->flags & CLK_IS_MEASURE))
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return 1;
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WARN_ON(!meas->post_div_val);
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div_val = meas->post_div_val;
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if (meas->pre_div_vals) {
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int i = clk_debug_mux_get_parent(mux);
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div_val *= meas->pre_div_vals[i];
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}
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parent = clk_hw_get_parent(mux);
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return div_val * get_mux_divs(parent);
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}
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static int clk_debug_measure_get(void *data, u64 *val)
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{
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struct clk_hw *hw = data, *par;
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struct clk_debug_mux *meas = to_clk_measure(measure);
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int index;
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struct clk_hw *hw = data;
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int ret = 0;
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unsigned long meas_rate, sw_rate;
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mutex_lock(&clk_debug_lock);
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ret = clk_set_parent(measure->clk, hw->clk);
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if (!ret) {
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par = measure;
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index = clk_debug_mux_get_parent(measure);
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enable_debug_clks(meas, index);
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while (par && par != hw) {
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if (par->init->ops->enable)
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par->init->ops->enable(par);
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par = clk_hw_get_parent(par);
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}
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*val = clk_debug_mux_measure_rate(measure);
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if (meas->parent[index].dbg_cc != GCC)
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*val *= meas->parent[index].post_div_val;
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*val *= meas->parent[index].prim_mux_div_val;
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/* Accommodate for any pre-set dividers */
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if (meas->parent[index].misc_div_val)
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*val *= meas->parent[index].misc_div_val;
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} else {
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ret = clk_find_and_set_parent(measure, hw);
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if (ret) {
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pr_err("Failed to set the debug mux's parent.\n");
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goto exit;
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}
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meas_rate = clk_get_rate(hw->clk);
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par = clk_hw_get_parent(measure);
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if (!par) {
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ret = -EINVAL;
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goto exit1;
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}
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enable_debug_clks(measure);
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*val = clk_debug_mux_measure_rate(measure);
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sw_rate = clk_get_rate(par->clk);
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if (sw_rate && meas_rate >= (sw_rate * 2))
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*val *= DIV_ROUND_CLOSEST(meas_rate, sw_rate);
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exit1:
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disable_debug_clks(meas, index);
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/* recursively calculate actual freq */
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*val *= get_mux_divs(measure);
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disable_debug_clks(measure);
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exit:
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mutex_unlock(&clk_debug_lock);
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return ret;
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@ -288,23 +272,74 @@ exit:
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DEFINE_DEBUGFS_ATTRIBUTE(clk_measure_fops, clk_debug_measure_get,
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NULL, "%lld\n");
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static int clk_debug_read_period(void *data, u64 *val)
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{
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struct clk_hw *hw = data;
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struct clk_hw *parent;
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struct clk_debug_mux *mux;
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int ret = 0;
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u32 regval;
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mutex_lock(&clk_debug_lock);
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ret = clk_find_and_set_parent(measure, hw);
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if (!ret) {
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parent = clk_hw_get_parent(measure);
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if (!parent) {
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mutex_unlock(&clk_debug_lock);
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return -EINVAL;
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}
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mux = to_clk_measure(parent);
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regmap_read(mux->regmap, mux->period_offset, ®val);
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if (!regval) {
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pr_err("Error reading mccc period register, ret = %d\n",
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ret);
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mutex_unlock(&clk_debug_lock);
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return 0;
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}
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*val = 1000000000000UL;
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do_div(*val, regval);
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} else {
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pr_err("Failed to set the debug mux's parent.\n");
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}
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mutex_unlock(&clk_debug_lock);
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return ret;
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}
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DEFINE_SIMPLE_ATTRIBUTE(clk_read_period_fops, clk_debug_read_period,
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NULL, "%lld\n");
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void clk_debug_measure_add(struct clk_hw *hw, struct dentry *dentry)
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{
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int ret;
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struct clk_hw *parent;
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struct clk_debug_mux *meas;
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struct clk_debug_mux *meas_parent;
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if (IS_ERR_OR_NULL(measure)) {
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pr_err_once("Please check if `measure` clk is registered.\n");
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return;
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}
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ret = clk_set_parent(measure->clk, hw->clk);
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meas = to_clk_measure(measure);
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ret = clk_find_and_set_parent(measure, hw);
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if (ret) {
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pr_debug("Unable to set %s as %s's parent, ret=%d\n",
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clk_hw_get_name(hw), clk_hw_get_name(measure), ret);
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return;
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}
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debugfs_create_file("clk_measure", 0444, dentry, hw,
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parent = clk_hw_get_parent(measure);
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if (!parent)
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return;
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meas_parent = to_clk_measure(parent);
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|
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if (parent->init->flags & CLK_IS_MEASURE && !meas_parent->mux_sels)
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debugfs_create_file("clk_measure", 0444, dentry, hw,
|
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&clk_read_period_fops);
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else
|
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debugfs_create_file("clk_measure", 0444, dentry, hw,
|
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&clk_measure_fops);
|
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}
|
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EXPORT_SYMBOL(clk_debug_measure_add);
|
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|
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@ -323,3 +358,31 @@ int clk_debug_measure_register(struct clk_hw *hw)
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}
|
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EXPORT_SYMBOL(clk_debug_measure_register);
|
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|
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/**
|
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* map_debug_bases - maps each debug mux based on phandle
|
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* @pdev: the platform device used to find phandles
|
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* @base: regmap base name used to look up phandle
|
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* @mux: debug mux that requires a regmap
|
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*
|
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* This function attempts to look up and map a regmap for a debug mux
|
||||
* using syscon_regmap_lookup_by_phandle if the base name property exists
|
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* and assigns an appropriate regmap.
|
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*
|
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* Returns 0 on success, -EBADR when it can't find base name, -EERROR otherwise.
|
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*/
|
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int map_debug_bases(struct platform_device *pdev, const char *base,
|
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struct clk_debug_mux *mux)
|
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{
|
||||
if (!of_get_property(pdev->dev.of_node, base, NULL))
|
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return -EBADR;
|
||||
|
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mux->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
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base);
|
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if (IS_ERR(mux->regmap)) {
|
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pr_err("Failed to map %s (ret=%ld)\n", base,
|
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PTR_ERR(mux->regmap));
|
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return PTR_ERR(mux->regmap);
|
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}
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(map_debug_bases);
|
||||
|
|
|
|||
|
|
@ -4,8 +4,20 @@
|
|||
#ifndef __QCOM_CLK_DEBUG_H__
|
||||
#define __QCOM_CLK_DEBUG_H__
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include "../clk.h"
|
||||
|
||||
/**
|
||||
* struct mux_regmap_names - Structure of mux regmap mapping
|
||||
* @mux: pointer to a clock debug mux
|
||||
* @regmap_name: corresponding regmap name used to match a debug mux to
|
||||
its regmap
|
||||
*/
|
||||
struct mux_regmap_names {
|
||||
struct clk_debug_mux *mux;
|
||||
const char *regmap_name;
|
||||
};
|
||||
|
||||
/* Debugfs Measure Clocks */
|
||||
|
||||
/**
|
||||
|
|
@ -24,67 +36,12 @@ struct measure_clk_data {
|
|||
u32 xo_div4_cbcr;
|
||||
};
|
||||
|
||||
/**
|
||||
* List of Debug clock controllers.
|
||||
*/
|
||||
enum debug_cc {
|
||||
GCC,
|
||||
CAM_CC,
|
||||
DISP_CC,
|
||||
NPU_CC,
|
||||
GPU_CC,
|
||||
VIDEO_CC,
|
||||
CPU_CC,
|
||||
MAX_NUM_CC,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clk_src - Structure of clock source for debug mux
|
||||
*
|
||||
* @parents: clock name to be used as parent for debug mux.
|
||||
* @prim_mux_sel: debug mux index at global clock controller.
|
||||
* @prim_mux_div_val: PLL post-divider setting for the primary mux.
|
||||
* @dbg_cc: indicates the clock controller for recursive debug
|
||||
* clock controllers.
|
||||
* @dbg_cc_mux_sel: indicates the debug mux index at recursive debug mux.
|
||||
* @mux_sel_mask: indicates the mask for the mux selection.
|
||||
* @mux_sel_shift: indicates the shift required for mux selection.
|
||||
* @post_div_mask: indicates the post div mask to be used at recursive
|
||||
* debug mux.
|
||||
* @post_div_shift: indicates the shift required for post divider
|
||||
* configuration.
|
||||
* @post_div_val: indicates the post div value to be used at recursive
|
||||
* debug mux.
|
||||
* @mux_offset: the debug mux offset.
|
||||
* @post_div_offset: register with post-divider settings for the debug mux.
|
||||
* @cbcr_offset: branch register to turn on debug mux.
|
||||
* @misc_div_val: includes any pre-set dividers in the measurement logic.
|
||||
*/
|
||||
struct clk_src {
|
||||
const char *parents;
|
||||
int prim_mux_sel;
|
||||
u32 prim_mux_div_val;
|
||||
enum debug_cc dbg_cc;
|
||||
int dbg_cc_mux_sel;
|
||||
u32 mux_sel_mask;
|
||||
u32 mux_sel_shift;
|
||||
u32 post_div_mask;
|
||||
u32 post_div_shift;
|
||||
u32 post_div_val;
|
||||
u32 mux_offset;
|
||||
u32 post_div_offset;
|
||||
u32 cbcr_offset;
|
||||
u32 misc_div_val;
|
||||
};
|
||||
|
||||
#define MUX_SRC_LIST(...) \
|
||||
.parent = (struct clk_src[]){__VA_ARGS__}, \
|
||||
.num_parents = ARRAY_SIZE(((struct clk_src[]){__VA_ARGS__}))
|
||||
|
||||
/**
|
||||
* struct clk_debug_mux - Structure of clock debug mux
|
||||
*
|
||||
* @parent: structure of clk_src
|
||||
* @mux_sels: indicates the debug mux index at recursive debug mux.
|
||||
* @pre_div_val: optional divider values for clocks that were pre-divided
|
||||
before feeding into the debug muxes
|
||||
* @num_parents: number of parents
|
||||
* @regmap: regmaps of debug mux
|
||||
* @priv: private measure_clk_data to be used by debug mux
|
||||
|
|
@ -101,21 +58,26 @@ struct clk_src {
|
|||
mux.
|
||||
* @post_div_shift: indicates the shift required for post divider
|
||||
selection in primary mux.
|
||||
* @period_offset: offset of the period register used to read to determine
|
||||
the mc clock period
|
||||
* @hw: handle between common and hardware-specific interfaces.
|
||||
*/
|
||||
struct clk_debug_mux {
|
||||
struct clk_src *parent;
|
||||
int *mux_sels;
|
||||
int *pre_div_vals;
|
||||
int num_parents;
|
||||
struct regmap **regmap;
|
||||
struct regmap *regmap;
|
||||
void *priv;
|
||||
u32 en_mask;
|
||||
u32 debug_offset;
|
||||
u32 post_div_offset;
|
||||
u32 cbcr_offset;
|
||||
u32 src_sel_mask;
|
||||
u32 src_sel_shift;
|
||||
u32 post_div_offset;
|
||||
u32 post_div_mask;
|
||||
u32 post_div_shift;
|
||||
u32 post_div_val;
|
||||
u32 period_offset;
|
||||
struct clk_hw hw;
|
||||
};
|
||||
|
||||
|
|
@ -125,5 +87,7 @@ extern const struct clk_ops clk_debug_mux_ops;
|
|||
|
||||
int clk_debug_measure_register(struct clk_hw *hw);
|
||||
void clk_debug_measure_add(struct clk_hw *hw, struct dentry *dentry);
|
||||
int map_debug_bases(struct platform_device *pdev, const char *base,
|
||||
struct clk_debug_mux *mux);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue