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Merge "fw-api: hw_headers: Add v1 e3r50 hw headers for wcn8750"

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QCTECMDR Service 2026-03-30 04:29:07 -07:00 • committed by Gerrit - the friendly Code Review server
commit a2b0e121c7
188 changed files with 59111 additions and 0 deletions
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39
hw/wcn8750/v1/HALcomdef.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef HAL_COMDEF_H
#define HAL_COMDEF_H
#ifndef _ARM_ASM_
#ifdef __cplusplus
extern "C" {
#endif
#include "com_dtypes.h"
#ifndef _BOOL32_DEFINED
typedef unsigned long int bool32;
#define _BOOL32_DEFINED
#endif
#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
#define inp(port) (*((volatile byte *) (port)))
#define inpw(port) (*((volatile word *) (port)))
#define inpdw(port) (*((volatile dword *)(port)))
#define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val)))
#define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
#define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
#ifdef __cplusplus
}
#endif
#endif
#endif

291
hw/wcn8750/v1/HALhwio.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef HAL_HWIO_H
#define HAL_HWIO_H
#include "HALcomdef.h"
#define HWIO_BASE_PTR(base) base##_BASE_PTR
#ifdef __ARMCC_VERSION
#define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
#else
#define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
#endif
#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val)
#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val)
#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
static uint32 Readdata, Val_temp, Val; \
Readdata = HWIO_INX(base, hwiosym); \
Val_temp = Readdata & ~mask1 & ~mask2; \
Val = Val_temp | val1 | val2; \
HWIO_##hwiosym##_OUT(base, Val); \
}
#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
static uint32 Readdata, Val_temp, Val; \
Readdata = HWIO_INX(base, hwiosym); \
Val_temp = Readdata & ~mask1 & ~mask2 & ~mask3; \
Val = Val_temp | val1 | val2 | val3; \
HWIO_##hwiosym##_OUT(base, Val); \
}
#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
static uint32 Readdata, Val_temp, Val; \
Readdata = HWIO_INX(base, hwiosym); \
Val_temp = Readdata & ~mask1 & ~mask2 & ~mask3 & ~mask4; \
Val = Val_temp | val1 | val2 | val3 | val4; \
HWIO_##hwiosym##_OUT(base, Val); \
}
#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
#define HWIO_INTLOCK()
#define HWIO_INTFREE()
#define __inp(port) (*((volatile uint8 *) (port)))
#define __inpw(port) (*((volatile uint16 *) (port)))
#define __inpdw(port) (*((volatile uint32 *) (port)))
#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
#ifdef HAL_HWIO_EXTERNAL
#undef __inp
#undef __inpw
#undef __inpdw
#undef __outp
#undef __outpw
#undef __outpdw
#define __inp(port) __inp_extern(port)
#define __inpw(port) __inpw_extern(port)
#define __inpdw(port) __inpdw_extern(port)
#define __outp(port, val) __outp_extern(port, val)
#define __outpw(port, val) __outpw_extern(port, val)
#define __outpdw(port, val) __outpdw_extern(port, val)
extern uint8 __inp_extern ( uint32 nAddr );
extern uint16 __inpw_extern ( uint32 nAddr );
extern uint32 __inpdw_extern ( uint32 nAddr );
extern void __outp_extern ( uint32 nAddr, uint8 nData );
extern void __outpw_extern ( uint32 nAddr, uint16 nData );
extern void __outpdw_extern ( uint32 nAddr, uint32 nData );
#endif
#define in_byte(addr) (__inp(addr))
#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
#define out_byte(addr, val) __outp(addr,val)
#define out_byte_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
out_byte( io, shadow); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
HWIO_INTFREE()
#define out_byte_masked_ns(io, mask, val, current_reg_content) \
out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))) )
#define in_word(addr) (__inpw(addr))
#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
#define out_word(addr, val) __outpw(addr,val)
#define out_word_masked(io, mask, val, shadow) \
HWIO_INTLOCK( ); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
out_word( io, shadow); \
HWIO_INTFREE( )
#define out_word_masked_ns(io, mask, val, current_reg_content) \
out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))) )
#define in_dword(addr) (__inpdw(addr))
#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
#define out_dword(addr, val) __outpdw(addr,val)
#define out_dword_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
out_dword( io, shadow); \
HWIO_INTFREE()
#define out_dword_masked_ns(io, mask, val, current_reg_content) \
out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
((uint32)((val) & (mask)))) )
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _ACK_REPORT_H_
#define _ACK_REPORT_H_
#define NUM_OF_DWORDS_ACK_REPORT 1
struct ack_report {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t selfgen_response_reason : 4,
ax_trigger_type : 4,
sr_ppdu : 1,
reserved : 7,
frame_control : 16;
#else
uint32_t frame_control : 16,
reserved : 7,
sr_ppdu : 1,
ax_trigger_type : 4,
selfgen_response_reason : 4;
#endif
};
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f
#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000
#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4
#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7
#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0
#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000
#define ACK_REPORT_SR_PPDU_LSB 8
#define ACK_REPORT_SR_PPDU_MSB 8
#define ACK_REPORT_SR_PPDU_MASK 0x00000100
#define ACK_REPORT_RESERVED_OFFSET 0x00000000
#define ACK_REPORT_RESERVED_LSB 9
#define ACK_REPORT_RESERVED_MSB 15
#define ACK_REPORT_RESERVED_MASK 0x0000fe00
#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
#define ACK_REPORT_FRAME_CONTROL_LSB 16
#define ACK_REPORT_FRAME_CONTROL_MSB 31
#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
#endif

12
hw/wcn8750/v1/boron_top_reg.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef BORON_TOP_REG_H
#define BORON_TOP_REG_H
#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C)
#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050)
#endif

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hw/wcn8750/v1/buffer_addr_info.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _BUFFER_ADDR_INFO_H_
#define _BUFFER_ADDR_INFO_H_
#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
struct buffer_addr_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t buffer_addr_31_0 : 32;
uint32_t buffer_addr_39_32 : 8,
return_buffer_manager : 4,
sw_buffer_cookie : 20;
#else
uint32_t buffer_addr_31_0 : 32;
uint32_t sw_buffer_cookie : 20,
return_buffer_manager : 4,
buffer_addr_39_32 : 8;
#endif
};
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _CE_SRC_DESC_H_
#define _CE_SRC_DESC_H_
#define NUM_OF_DWORDS_CE_SRC_DESC 4
struct ce_src_desc {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t src_buffer_low : 32;
uint32_t src_buffer_high : 8,
toeplitz_en : 1,
src_swap : 1,
dest_swap : 1,
gather : 1,
ce_res_0 : 1,
barrier_read : 1,
ce_res_1 : 2,
length : 16;
uint32_t fw_metadata : 16,
ce_res_2 : 16;
uint32_t ce_res_3 : 20,
ring_id : 8,
looping_count : 4;
#else
uint32_t src_buffer_low : 32;
uint32_t length : 16,
ce_res_1 : 2,
barrier_read : 1,
ce_res_0 : 1,
gather : 1,
dest_swap : 1,
src_swap : 1,
toeplitz_en : 1,
src_buffer_high : 8;
uint32_t ce_res_2 : 16,
fw_metadata : 16;
uint32_t looping_count : 4,
ring_id : 8,
ce_res_3 : 20;
#endif
};
#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000
#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0
#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31
#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff
#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004
#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff
#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004
#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8
#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8
#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100
#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_SRC_SWAP_LSB 9
#define CE_SRC_DESC_SRC_SWAP_MSB 9
#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200
#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_DEST_SWAP_LSB 10
#define CE_SRC_DESC_DEST_SWAP_MSB 10
#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400
#define CE_SRC_DESC_GATHER_OFFSET 0x00000004
#define CE_SRC_DESC_GATHER_LSB 11
#define CE_SRC_DESC_GATHER_MSB 11
#define CE_SRC_DESC_GATHER_MASK 0x00000800
#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004
#define CE_SRC_DESC_CE_RES_0_LSB 12
#define CE_SRC_DESC_CE_RES_0_MSB 12
#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000
#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004
#define CE_SRC_DESC_BARRIER_READ_LSB 13
#define CE_SRC_DESC_BARRIER_READ_MSB 13
#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000
#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004
#define CE_SRC_DESC_CE_RES_1_LSB 14
#define CE_SRC_DESC_CE_RES_1_MSB 15
#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000
#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004
#define CE_SRC_DESC_LENGTH_LSB 16
#define CE_SRC_DESC_LENGTH_MSB 31
#define CE_SRC_DESC_LENGTH_MASK 0xffff0000
#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008
#define CE_SRC_DESC_FW_METADATA_LSB 0
#define CE_SRC_DESC_FW_METADATA_MSB 15
#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff
#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008
#define CE_SRC_DESC_CE_RES_2_LSB 16
#define CE_SRC_DESC_CE_RES_2_MSB 31
#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000
#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c
#define CE_SRC_DESC_CE_RES_3_LSB 0
#define CE_SRC_DESC_CE_RES_3_MSB 19
#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff
#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c
#define CE_SRC_DESC_RING_ID_LSB 20
#define CE_SRC_DESC_RING_ID_MSB 27
#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000
#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_SRC_DESC_LOOPING_COUNT_LSB 28
#define CE_SRC_DESC_LOOPING_COUNT_MSB 31
#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _CE_STAT_DESC_H_
#define _CE_STAT_DESC_H_
#define NUM_OF_DWORDS_CE_STAT_DESC 4
struct ce_stat_desc {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t ce_res_5 : 8,
toeplitz_en : 1,
src_swap : 1,
dest_swap : 1,
gather : 1,
barrier_read : 1,
ce_res_6 : 3,
length : 16;
uint32_t toeplitz_hash_0 : 32;
uint32_t toeplitz_hash_1 : 32;
uint32_t fw_metadata : 16,
ce_res_7 : 4,
ring_id : 8,
looping_count : 4;
#else
uint32_t length : 16,
ce_res_6 : 3,
barrier_read : 1,
gather : 1,
dest_swap : 1,
src_swap : 1,
toeplitz_en : 1,
ce_res_5 : 8;
uint32_t toeplitz_hash_0 : 32;
uint32_t toeplitz_hash_1 : 32;
uint32_t looping_count : 4,
ring_id : 8,
ce_res_7 : 4,
fw_metadata : 16;
#endif
};
#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000
#define CE_STAT_DESC_CE_RES_5_LSB 0
#define CE_STAT_DESC_CE_RES_5_MSB 7
#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff
#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000
#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8
#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8
#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100
#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_SRC_SWAP_LSB 9
#define CE_STAT_DESC_SRC_SWAP_MSB 9
#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200
#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_DEST_SWAP_LSB 10
#define CE_STAT_DESC_DEST_SWAP_MSB 10
#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400
#define CE_STAT_DESC_GATHER_OFFSET 0x00000000
#define CE_STAT_DESC_GATHER_LSB 11
#define CE_STAT_DESC_GATHER_MSB 11
#define CE_STAT_DESC_GATHER_MASK 0x00000800
#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000
#define CE_STAT_DESC_BARRIER_READ_LSB 12
#define CE_STAT_DESC_BARRIER_READ_MSB 12
#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000
#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000
#define CE_STAT_DESC_CE_RES_6_LSB 13
#define CE_STAT_DESC_CE_RES_6_MSB 15
#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000
#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000
#define CE_STAT_DESC_LENGTH_LSB 16
#define CE_STAT_DESC_LENGTH_MSB 31
#define CE_STAT_DESC_LENGTH_MASK 0xffff0000
#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004
#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff
#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008
#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff
#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c
#define CE_STAT_DESC_FW_METADATA_LSB 0
#define CE_STAT_DESC_FW_METADATA_MSB 15
#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff
#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c
#define CE_STAT_DESC_CE_RES_7_LSB 16
#define CE_STAT_DESC_CE_RES_7_MSB 19
#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000
#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c
#define CE_STAT_DESC_RING_ID_LSB 20
#define CE_STAT_DESC_RING_ID_MSB 27
#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000
#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_STAT_DESC_LOOPING_COUNT_LSB 28
#define CE_STAT_DESC_LOOPING_COUNT_MSB 31
#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000
#endif

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hw/wcn8750/v1/coex_rx_status.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _COEX_RX_STATUS_H_
#define _COEX_RX_STATUS_H_
#define NUM_OF_DWORDS_COEX_RX_STATUS 2
#define NUM_OF_QWORDS_COEX_RX_STATUS 1
struct coex_rx_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t rx_mac_frame_status : 2,
rx_with_tx_response : 1,
rx_rate : 5,
rx_bw : 3,
single_mpdu : 1,
filter_status : 1,
ampdu : 1,
directed : 1,
reserved_0 : 1,
rx_nss : 3,
rx_rssi : 8,
rx_type : 3,
retry_bit_setting : 1,
more_data_bit_setting : 1;
uint32_t remain_rx_packet_time : 16,
rx_remaining_fes_time : 16;
#else
uint32_t more_data_bit_setting : 1,
retry_bit_setting : 1,
rx_type : 3,
rx_rssi : 8,
rx_nss : 3,
reserved_0 : 1,
directed : 1,
ampdu : 1,
filter_status : 1,
single_mpdu : 1,
rx_bw : 3,
rx_rate : 5,
rx_with_tx_response : 1,
rx_mac_frame_status : 2;
uint32_t rx_remaining_fes_time : 16,
remain_rx_packet_time : 16;
#endif
};
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004
#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RX_RATE_LSB 3
#define COEX_RX_STATUS_RX_RATE_MSB 7
#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8
#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RX_BW_LSB 8
#define COEX_RX_STATUS_RX_BW_MSB 10
#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700
#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11
#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11
#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800
#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_FILTER_STATUS_LSB 12
#define COEX_RX_STATUS_FILTER_STATUS_MSB 12
#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000
#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_AMPDU_LSB 13
#define COEX_RX_STATUS_AMPDU_MSB 13
#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000
#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_DIRECTED_LSB 14
#define COEX_RX_STATUS_DIRECTED_MSB 14
#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000
#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RESERVED_0_LSB 15
#define COEX_RX_STATUS_RESERVED_0_MSB 15
#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000
#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RX_NSS_LSB 16
#define COEX_RX_STATUS_RX_NSS_MSB 18
#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000
#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RX_RSSI_LSB 19
#define COEX_RX_STATUS_RX_RSSI_MSB 26
#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000
#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RX_TYPE_LSB 27
#define COEX_RX_STATUS_RX_TYPE_MSB 29
#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000
#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30
#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30
#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _COEX_TX_REQ_H_
#define _COEX_TX_REQ_H_
#define NUM_OF_DWORDS_COEX_TX_REQ 6
#define NUM_OF_QWORDS_COEX_TX_REQ 3
struct coex_tx_req {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t tx_pwr : 8,
min_tx_pwr : 8,
nss : 3,
tx_chain_mask : 8,
bw : 3,
reserved_0 : 2;
uint32_t alt_tx_pwr : 8,
alt_min_tx_pwr : 8,
alt_nss : 3,
alt_tx_chain_mask : 8,
alt_bw : 3,
reserved_1 : 2;
uint32_t tx_pwr_1 : 8,
alt_tx_pwr_1 : 8,
wlan_request_duration : 16;
uint32_t wlan_pkt_type : 4,
coex_tx_reason : 2,
response_frame_type : 5,
wlan_low_priority_slicing_allowed : 1,
wlan_high_priority_slicing_allowed : 1,
sch_tx_burst_ongoing : 1,
coex_tx_priority : 4,
blackout_details_en : 1,
blackout_peek_duration : 8,
reserved_3a : 5;
uint32_t frequency_channel_bonding_mask : 16,
num_blackout_windows : 8,
reserved_4a : 8;
uint32_t tlv64_padding : 32;
#else
uint32_t reserved_0 : 2,
bw : 3,
tx_chain_mask : 8,
nss : 3,
min_tx_pwr : 8,
tx_pwr : 8;
uint32_t reserved_1 : 2,
alt_bw : 3,
alt_tx_chain_mask : 8,
alt_nss : 3,
alt_min_tx_pwr : 8,
alt_tx_pwr : 8;
uint32_t wlan_request_duration : 16,
alt_tx_pwr_1 : 8,
tx_pwr_1 : 8;
uint32_t reserved_3a : 5,
blackout_peek_duration : 8,
blackout_details_en : 1,
coex_tx_priority : 4,
sch_tx_burst_ongoing : 1,
wlan_high_priority_slicing_allowed : 1,
wlan_low_priority_slicing_allowed : 1,
response_frame_type : 5,
coex_tx_reason : 2,
wlan_pkt_type : 4;
uint32_t reserved_4a : 8,
num_blackout_windows : 8,
frequency_channel_bonding_mask : 16;
uint32_t tlv64_padding : 32;
#endif
};
#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000
#define COEX_TX_REQ_TX_PWR_LSB 0
#define COEX_TX_REQ_TX_PWR_MSB 7
#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff
#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000
#define COEX_TX_REQ_MIN_TX_PWR_LSB 8
#define COEX_TX_REQ_MIN_TX_PWR_MSB 15
#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00
#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000
#define COEX_TX_REQ_NSS_LSB 16
#define COEX_TX_REQ_NSS_MSB 18
#define COEX_TX_REQ_NSS_MASK 0x0000000000070000
#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000
#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19
#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26
#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000
#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000
#define COEX_TX_REQ_BW_LSB 27
#define COEX_TX_REQ_BW_MSB 29
#define COEX_TX_REQ_BW_MASK 0x0000000038000000
#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000
#define COEX_TX_REQ_RESERVED_0_LSB 30
#define COEX_TX_REQ_RESERVED_0_MSB 31
#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000
#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000
#define COEX_TX_REQ_ALT_TX_PWR_LSB 32
#define COEX_TX_REQ_ALT_TX_PWR_MSB 39
#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000
#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000
#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40
#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47
#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000
#define COEX_TX_REQ_ALT_NSS_LSB 48
#define COEX_TX_REQ_ALT_NSS_MSB 50
#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000
#define COEX_TX_REQ_ALT_BW_LSB 59
#define COEX_TX_REQ_ALT_BW_MSB 61
#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000
#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000
#define COEX_TX_REQ_RESERVED_1_LSB 62
#define COEX_TX_REQ_RESERVED_1_MSB 63
#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000
#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008
#define COEX_TX_REQ_TX_PWR_1_LSB 0
#define COEX_TX_REQ_TX_PWR_1_MSB 7
#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff
#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008
#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8
#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15
#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000
#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008
#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32
#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35
#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000
#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008
#define COEX_TX_REQ_COEX_TX_REASON_LSB 36
#define COEX_TX_REQ_COEX_TX_REASON_MSB 37
#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000
#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008
#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46
#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49
#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000
#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000008
#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB 50
#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB 50
#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK 0x0004000000000000
#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET 0x0000000000000008
#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB 51
#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB 58
#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK 0x07f8000000000000
#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008
#define COEX_TX_REQ_RESERVED_3A_LSB 59
#define COEX_TX_REQ_RESERVED_3A_MSB 63
#define COEX_TX_REQ_RESERVED_3A_MASK 0xf800000000000000
#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000010
#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB 0
#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB 15
#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK 0x000000000000ffff
#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET 0x0000000000000010
#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB 16
#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB 23
#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK 0x0000000000ff0000
#define COEX_TX_REQ_RESERVED_4A_OFFSET 0x0000000000000010
#define COEX_TX_REQ_RESERVED_4A_LSB 24
#define COEX_TX_REQ_RESERVED_4A_MSB 31
#define COEX_TX_REQ_RESERVED_4A_MASK 0x00000000ff000000
#define COEX_TX_REQ_TLV64_PADDING_OFFSET 0x0000000000000010
#define COEX_TX_REQ_TLV64_PADDING_LSB 32
#define COEX_TX_REQ_TLV64_PADDING_MSB 63
#define COEX_TX_REQ_TLV64_PADDING_MASK 0xffffffff00000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _COEX_TX_STATUS_H_
#define _COEX_TX_STATUS_H_
#define NUM_OF_DWORDS_COEX_TX_STATUS 4
#define NUM_OF_QWORDS_COEX_TX_STATUS 2
struct coex_tx_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t reserved_0a : 7,
tx_bw : 3,
tx_status_reason : 3,
tx_wait_ack : 1,
fes_tx_is_gen_frame : 1,
sch_tx_burst_ongoing : 1,
current_tx_duration : 16;
uint32_t next_rx_active_time : 16,
remaining_fes_time : 16;
uint32_t tx_antenna_mask : 8,
shared_ant_tx_pwr : 8,
other_ant_tx_pwr : 8,
reserved_2 : 8;
uint32_t tlv64_padding : 32;
#else
uint32_t current_tx_duration : 16,
sch_tx_burst_ongoing : 1,
fes_tx_is_gen_frame : 1,
tx_wait_ack : 1,
tx_status_reason : 3,
tx_bw : 3,
reserved_0a : 7;
uint32_t remaining_fes_time : 16,
next_rx_active_time : 16;
uint32_t reserved_2 : 8,
other_ant_tx_pwr : 8,
shared_ant_tx_pwr : 8,
tx_antenna_mask : 8;
uint32_t tlv64_padding : 32;
#endif
};
#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000
#define COEX_TX_STATUS_RESERVED_0A_LSB 0
#define COEX_TX_STATUS_RESERVED_0A_MSB 6
#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f
#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000
#define COEX_TX_STATUS_TX_BW_LSB 7
#define COEX_TX_STATUS_TX_BW_MSB 9
#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380
#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000
#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10
#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12
#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00
#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000
#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13
#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13
#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000
#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000
#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16
#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31
#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000
#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000
#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48
#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63
#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000
#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008
#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0
#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7
#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000
#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008
#define COEX_TX_STATUS_RESERVED_2_LSB 24
#define COEX_TX_STATUS_RESERVED_2_MSB 31
#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000
#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008
#define COEX_TX_STATUS_TLV64_PADDING_LSB 32
#define COEX_TX_STATUS_TLV64_PADDING_MSB 63
#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef COM_DTYPES_H
#define COM_DTYPES_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef T_WINNT
#ifndef WIN32
#define WIN32
#endif
#include <stdlib.h>
#endif
#ifdef TRUE
#undef TRUE
#endif
#ifdef FALSE
#undef FALSE
#endif
#define TRUE 1
#define FALSE 0
#define ON 1
#define OFF 0
#ifndef NULL
#define NULL 0
#endif
#ifndef _ARM_ASM_
#ifndef _BOOLEAN_DEFINED
typedef unsigned char boolean;
#define _BOOLEAN_DEFINED
#endif
#if defined(DALSTDDEF_H)
#define _BOOLEAN_DEFINED
#define _UINT32_DEFINED
#define _UINT16_DEFINED
#define _UINT8_DEFINED
#define _INT32_DEFINED
#define _INT16_DEFINED
#define _INT8_DEFINED
#define _UINT64_DEFINED
#define _INT64_DEFINED
#define _BYTE_DEFINED
#endif
#ifndef _UINT32_DEFINED
typedef unsigned int uint32;
#define _UINT32_DEFINED
#endif
#ifndef _UINT16_DEFINED
typedef unsigned short uint16;
#define _UINT16_DEFINED
#endif
#ifndef _UINT8_DEFINED
typedef unsigned char uint8;
#define _UINT8_DEFINED
#endif
#ifndef _INT32_DEFINED
typedef signed int int32;
#define _INT32_DEFINED
#endif
#ifndef _INT16_DEFINED
typedef signed short int16;
#define _INT16_DEFINED
#endif
#ifndef _INT8_DEFINED
typedef signed char int8;
#define _INT8_DEFINED
#endif
#ifndef _BYTE_DEFINED
typedef unsigned char byte;
#define _BYTE_DEFINED
#endif
typedef unsigned short word;
typedef unsigned long dword;
typedef unsigned char uint1;
typedef unsigned short uint2;
typedef unsigned long uint4;
typedef signed char int1;
typedef signed short int2;
typedef long int int4;
typedef signed long sint31;
typedef signed short sint15;
typedef signed char sint7;
typedef uint16 UWord16 ;
typedef uint32 UWord32 ;
typedef int32 Word32 ;
typedef int16 Word16 ;
typedef uint8 UWord8 ;
typedef int8 Word8 ;
typedef int32 Vect32 ;
#if (! defined T_WINNT) && (! defined __GNUC__)
#ifndef _INT64_DEFINED
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else
#if (defined __GNUC__)
#ifndef _INT64_DEFINED
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else
typedef __int64 int64;
#ifndef _UINT64_DEFINED
typedef unsigned __int64 uint64;
#define _UINT64_DEFINED
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

94
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
#define _EHT_SIG_USR_MU_MIMO_INFO_H_
#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
struct eht_sig_usr_mu_mimo_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t sta_id : 11,
sta_mcs : 4,
sta_coding : 1,
sta_spatial_config : 6,
reserved_0a : 1,
rx_integrity_check_passed : 1,
subband80_cc_mask : 8;
uint32_t user_order_subband80_0 : 8,
user_order_subband80_1 : 8,
user_order_subband80_2 : 8,
user_order_subband80_3 : 8;
#else
uint32_t subband80_cc_mask : 8,
rx_integrity_check_passed : 1,
reserved_0a : 1,
sta_spatial_config : 6,
sta_coding : 1,
sta_mcs : 4,
sta_id : 11;
uint32_t user_order_subband80_3 : 8,
user_order_subband80_2 : 8,
user_order_subband80_1 : 8,
user_order_subband80_0 : 8;
#endif
};
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
#define _EHT_SIG_USR_OFDMA_INFO_H_
#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
struct eht_sig_usr_ofdma_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t sta_id : 11,
sta_mcs : 4,
validate_0a : 1,
nss : 4,
txbf : 1,
sta_coding : 1,
reserved_0b : 1,
rx_integrity_check_passed : 1,
subband80_cc_mask : 8;
uint32_t user_order_subband80_0 : 8,
user_order_subband80_1 : 8,
user_order_subband80_2 : 8,
user_order_subband80_3 : 8;
#else
uint32_t subband80_cc_mask : 8,
rx_integrity_check_passed : 1,
reserved_0b : 1,
sta_coding : 1,
txbf : 1,
nss : 4,
validate_0a : 1,
sta_mcs : 4,
sta_id : 11;
uint32_t user_order_subband80_3 : 8,
user_order_subband80_2 : 8,
user_order_subband80_1 : 8,
user_order_subband80_0 : 8;
#endif
};
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000
#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000
#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16
#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19
#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000
#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000
#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _EHT_SIG_USR_SU_INFO_H_
#define _EHT_SIG_USR_SU_INFO_H_
#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
struct eht_sig_usr_su_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t sta_id : 11,
sta_mcs : 4,
validate_0a : 1,
nss : 4,
txbf : 1,
sta_coding : 1,
reserved_0b : 9,
rx_integrity_check_passed : 1;
#else
uint32_t rx_integrity_check_passed : 1,
reserved_0b : 9,
sta_coding : 1,
txbf : 1,
nss : 4,
validate_0a : 1,
sta_mcs : 4,
sta_id : 11;
#endif
};
#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000
#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0
#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10
#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff
#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000
#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11
#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14
#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000
#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000
#define EHT_SIG_USR_SU_INFO_NSS_LSB 16
#define EHT_SIG_USR_SU_INFO_NSS_MSB 19
#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000
#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000
#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20
#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20
#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000
#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000
#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21
#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21
#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _EXPECTED_RESPONSE_H_
#define _EXPECTED_RESPONSE_H_
#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6
#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3
struct expected_response {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t tx_ad2_31_0 : 32;
uint32_t tx_ad2_47_32 : 16,
expected_response_type : 5,
response_to_response : 3,
su_ba_user_number : 1,
response_info_part2_required : 1,
transmitted_bssid_check_en : 1,
eht___reserved_g_0005_ndp_expected : 1,
reserved_1 : 4;
uint32_t ndp_sta_partial_aid_2_8_0 : 11,
reserved_2 : 10,
ndp_sta_partial_aid1_8_0 : 11;
uint32_t ast_index : 16,
capture_ack_ba_sounding : 1,
capture_sounding_1str_20mhz : 1,
capture_sounding_1str_40mhz : 1,
capture_sounding_1str_80mhz : 1,
capture_sounding_1str_160mhz : 1,
capture_sounding_1str_240mhz : 1,
capture_sounding_1str_320mhz : 1,
reserved_3a : 9;
uint32_t fcs : 9,
expect_rx_with_blackout_details : 1,
crc : 4,
scrambler_seed : 7,
reserved_4b : 11;
uint32_t tlv64_padding : 32;
#else
uint32_t tx_ad2_31_0 : 32;
uint32_t reserved_1 : 4,
eht___reserved_g_0005_ndp_expected : 1,
transmitted_bssid_check_en : 1,
response_info_part2_required : 1,
su_ba_user_number : 1,
response_to_response : 3,
expected_response_type : 5,
tx_ad2_47_32 : 16;
uint32_t ndp_sta_partial_aid1_8_0 : 11,
reserved_2 : 10,
ndp_sta_partial_aid_2_8_0 : 11;
uint32_t reserved_3a : 9,
capture_sounding_1str_320mhz : 1,
capture_sounding_1str_240mhz : 1,
capture_sounding_1str_160mhz : 1,
capture_sounding_1str_80mhz : 1,
capture_sounding_1str_40mhz : 1,
capture_sounding_1str_20mhz : 1,
capture_ack_ba_sounding : 1,
ast_index : 16;
uint32_t reserved_4b : 11,
scrambler_seed : 7,
crc : 4,
expect_rx_with_blackout_details : 1,
fcs : 9;
uint32_t tlv64_padding : 32;
#endif
};
#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000
#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0
#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31
#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff
#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000
#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32
#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47
#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000
#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000
#define EXPECTED_RESPONSE_RESERVED_1_LSB 60
#define EXPECTED_RESPONSE_RESERVED_1_MSB 63
#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf000000000000000
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff
#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_RESERVED_2_LSB 11
#define EXPECTED_RESPONSE_RESERVED_2_MSB 20
#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000
#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_AST_INDEX_LSB 32
#define EXPECTED_RESPONSE_AST_INDEX_MSB 47
#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000
#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008
#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55
#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63
#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000
#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010
#define EXPECTED_RESPONSE_FCS_LSB 0
#define EXPECTED_RESPONSE_FCS_MSB 8
#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff
#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x0000000000000010
#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 9
#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 9
#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000000000200
#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010
#define EXPECTED_RESPONSE_CRC_LSB 10
#define EXPECTED_RESPONSE_CRC_MSB 13
#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000
#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010
#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21
#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31
#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000
#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010
#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32
#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63
#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _HE_SIG_A_MU_DL_INFO_H_
#define _HE_SIG_A_MU_DL_INFO_H_
#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
struct he_sig_a_mu_dl_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t dl_ul_flag : 1,
mcs_of_sig_b : 3,
dcm_of_sig_b : 1,
bss_color_id : 6,
spatial_reuse : 4,
transmit_bw : 3,
num_sig_b_symbols : 4,
comp_mode_sig_b : 1,
cp_ltf_size : 2,
doppler_indication : 1,
reserved_0a : 6;
uint32_t txop_duration : 7,
reserved_1a : 1,
num_ltf_symbols : 3,
ldpc_extra_symbol : 1,
stbc : 1,
packet_extension_a_factor : 2,
packet_extension_pe_disambiguity : 1,
crc : 4,
tail : 6,
reserved_1b : 5,
rx_integrity_check_passed : 1;
#else
uint32_t reserved_0a : 6,
doppler_indication : 1,
cp_ltf_size : 2,
comp_mode_sig_b : 1,
num_sig_b_symbols : 4,
transmit_bw : 3,
spatial_reuse : 4,
bss_color_id : 6,
dcm_of_sig_b : 1,
mcs_of_sig_b : 3,
dl_ul_flag : 1;
uint32_t rx_integrity_check_passed : 1,
reserved_1b : 5,
tail : 6,
crc : 4,
packet_extension_pe_disambiguity : 1,
packet_extension_a_factor : 2,
stbc : 1,
ldpc_extra_symbol : 1,
num_ltf_symbols : 3,
reserved_1a : 1,
txop_duration : 7;
#endif
};
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800
#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12
#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12
#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16
#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19
#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000
#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20
#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25
#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _HE_SIG_A_MU_UL_INFO_H_
#define _HE_SIG_A_MU_UL_INFO_H_
#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
struct he_sig_a_mu_ul_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t format_indication : 1,
bss_color_id : 6,
spatial_reuse : 16,
reserved_0a : 1,
transmit_bw : 2,
reserved_0b : 6;
uint32_t txop_duration : 7,
reserved_1a : 9,
crc : 4,
tail : 6,
reserved_1b : 5,
rx_integrity_check_passed : 1;
#else
uint32_t reserved_0b : 6,
transmit_bw : 2,
reserved_0a : 1,
spatial_reuse : 16,
bss_color_id : 6,
format_indication : 1;
uint32_t rx_integrity_check_passed : 1,
reserved_1b : 5,
tail : 6,
crc : 4,
reserved_1a : 9,
txop_duration : 7;
#endif
};
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80
#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16
#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19
#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000
#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20
#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25
#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _HE_SIG_A_SU_INFO_H_
#define _HE_SIG_A_SU_INFO_H_
#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
struct he_sig_a_su_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t format_indication : 1,
beam_change : 1,
dl_ul_flag : 1,
transmit_mcs : 4,
dcm : 1,
bss_color_id : 6,
reserved_0a : 1,
spatial_reuse : 4,
transmit_bw : 2,
cp_ltf_size : 2,
nsts : 3,
reserved_0b : 6;
uint32_t txop_duration : 7,
coding : 1,
ldpc_extra_symbol : 1,
stbc : 1,
txbf : 1,
packet_extension_a_factor : 2,
packet_extension_pe_disambiguity : 1,
reserved_1a : 1,
doppler_indication : 1,
crc : 4,
tail : 6,
dot11ax_su_extended : 1,
dot11ax_ext_ru_size : 3,
rx_ndp : 1,
rx_integrity_check_passed : 1;
#else
uint32_t reserved_0b : 6,
nsts : 3,
cp_ltf_size : 2,
transmit_bw : 2,
spatial_reuse : 4,
reserved_0a : 1,
bss_color_id : 6,
dcm : 1,
transmit_mcs : 4,
dl_ul_flag : 1,
beam_change : 1,
format_indication : 1;
uint32_t rx_integrity_check_passed : 1,
rx_ndp : 1,
dot11ax_ext_ru_size : 3,
dot11ax_su_extended : 1,
tail : 6,
crc : 4,
doppler_indication : 1,
reserved_1a : 1,
packet_extension_pe_disambiguity : 1,
packet_extension_a_factor : 2,
txbf : 1,
stbc : 1,
ldpc_extra_symbol : 1,
coding : 1,
txop_duration : 7;
#endif
};
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078
#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_DCM_LSB 7
#define HE_SIG_A_SU_INFO_DCM_MSB 7
#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00
#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14
#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14
#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000
#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_NSTS_LSB 23
#define HE_SIG_A_SU_INFO_NSTS_MSB 25
#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000
#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26
#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31
#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000
#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f
#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_CODING_LSB 7
#define HE_SIG_A_SU_INFO_CODING_MSB 7
#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100
#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_STBC_LSB 9
#define HE_SIG_A_SU_INFO_STBC_MSB 9
#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200
#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_TXBF_LSB 10
#define HE_SIG_A_SU_INFO_TXBF_MSB 10
#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14
#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14
#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000
#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_CRC_LSB 16
#define HE_SIG_A_SU_INFO_CRC_MSB 19
#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000
#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_TAIL_LSB 20
#define HE_SIG_A_SU_INFO_TAIL_MSB 25
#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30
#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30
#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _HE_SIG_B1_MU_INFO_H_
#define _HE_SIG_B1_MU_INFO_H_
#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
struct he_sig_b1_mu_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t ru_allocation : 8,
reserved_0 : 23,
rx_integrity_check_passed : 1;
#else
uint32_t rx_integrity_check_passed : 1,
reserved_0 : 23,
ru_allocation : 8;
#endif
};
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff
#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8
#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30
#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _HE_SIG_B2_MU_INFO_H_
#define _HE_SIG_B2_MU_INFO_H_
#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
struct he_sig_b2_mu_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t sta_id : 11,
sta_spatial_config : 4,
sta_mcs : 4,
reserved_set_to_1 : 1,
sta_coding : 1,
reserved_0a : 7,
nsts : 3,
rx_integrity_check_passed : 1;
uint32_t user_order : 8,
cc_mask : 8,
reserved_1a : 16;
#else
uint32_t rx_integrity_check_passed : 1,
nsts : 3,
reserved_0a : 7,
sta_coding : 1,
reserved_set_to_1 : 1,
sta_mcs : 4,
sta_spatial_config : 4,
sta_id : 11;
uint32_t reserved_1a : 16,
cc_mask : 8,
user_order : 8;
#endif
};
#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0
#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10
#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800
#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15
#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18
#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000
#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20
#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20
#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000
#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000
#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_NSTS_LSB 28
#define HE_SIG_B2_MU_INFO_NSTS_MSB 30
#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004
#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0
#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7
#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff
#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004
#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8
#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15
#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00
#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _HE_SIG_B2_OFDMA_INFO_H_
#define _HE_SIG_B2_OFDMA_INFO_H_
#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
struct he_sig_b2_ofdma_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t sta_id : 11,
nsts : 3,
txbf : 1,
sta_mcs : 4,
sta_dcm : 1,
sta_coding : 1,
reserved_0 : 10,
rx_integrity_check_passed : 1;
uint32_t user_order : 8,
cc_mask : 8,
reserved_1a : 16;
#else
uint32_t rx_integrity_check_passed : 1,
reserved_0 : 10,
sta_coding : 1,
sta_dcm : 1,
sta_mcs : 4,
txbf : 1,
nsts : 3,
sta_id : 11;
uint32_t reserved_1a : 16,
cc_mask : 8,
user_order : 8;
#endif
};
#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff
#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11
#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13
#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800
#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14
#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14
#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _HT_SIG_INFO_H_
#define _HT_SIG_INFO_H_
#define NUM_OF_DWORDS_HT_SIG_INFO 2
struct ht_sig_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t mcs : 7,
cbw : 1,
length : 16,
reserved_0 : 8;
uint32_t smoothing : 1,
not_sounding : 1,
ht_reserved : 1,
aggregation : 1,
stbc : 2,
fec_coding : 1,
short_gi : 1,
num_ext_sp_str : 2,
crc : 8,
signal_tail : 6,
reserved_1 : 7,
rx_integrity_check_passed : 1;
#else
uint32_t reserved_0 : 8,
length : 16,
cbw : 1,
mcs : 7;
uint32_t rx_integrity_check_passed : 1,
reserved_1 : 7,
signal_tail : 6,
crc : 8,
num_ext_sp_str : 2,
short_gi : 1,
fec_coding : 1,
stbc : 2,
aggregation : 1,
ht_reserved : 1,
not_sounding : 1,
smoothing : 1;
#endif
};
#define HT_SIG_INFO_MCS_OFFSET 0x00000000
#define HT_SIG_INFO_MCS_LSB 0
#define HT_SIG_INFO_MCS_MSB 6
#define HT_SIG_INFO_MCS_MASK 0x0000007f
#define HT_SIG_INFO_CBW_OFFSET 0x00000000
#define HT_SIG_INFO_CBW_LSB 7
#define HT_SIG_INFO_CBW_MSB 7
#define HT_SIG_INFO_CBW_MASK 0x00000080
#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000
#define HT_SIG_INFO_LENGTH_LSB 8
#define HT_SIG_INFO_LENGTH_MSB 23
#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00
#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000
#define HT_SIG_INFO_RESERVED_0_LSB 24
#define HT_SIG_INFO_RESERVED_0_MSB 31
#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000
#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004
#define HT_SIG_INFO_SMOOTHING_LSB 0
#define HT_SIG_INFO_SMOOTHING_MSB 0
#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001
#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004
#define HT_SIG_INFO_NOT_SOUNDING_LSB 1
#define HT_SIG_INFO_NOT_SOUNDING_MSB 1
#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002
#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004
#define HT_SIG_INFO_HT_RESERVED_LSB 2
#define HT_SIG_INFO_HT_RESERVED_MSB 2
#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004
#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004
#define HT_SIG_INFO_AGGREGATION_LSB 3
#define HT_SIG_INFO_AGGREGATION_MSB 3
#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008
#define HT_SIG_INFO_STBC_OFFSET 0x00000004
#define HT_SIG_INFO_STBC_LSB 4
#define HT_SIG_INFO_STBC_MSB 5
#define HT_SIG_INFO_STBC_MASK 0x00000030
#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004
#define HT_SIG_INFO_FEC_CODING_LSB 6
#define HT_SIG_INFO_FEC_CODING_MSB 6
#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040
#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004
#define HT_SIG_INFO_SHORT_GI_LSB 7
#define HT_SIG_INFO_SHORT_GI_MSB 7
#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080
#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004
#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8
#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9
#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300
#define HT_SIG_INFO_CRC_OFFSET 0x00000004
#define HT_SIG_INFO_CRC_LSB 10
#define HT_SIG_INFO_CRC_MSB 17
#define HT_SIG_INFO_CRC_MASK 0x0003fc00
#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004
#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18
#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23
#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000
#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004
#define HT_SIG_INFO_RESERVED_1_LSB 24
#define HT_SIG_INFO_RESERVED_1_MSB 30
#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _L_SIG_A_INFO_H_
#define _L_SIG_A_INFO_H_
#define NUM_OF_DWORDS_L_SIG_A_INFO 1
struct l_sig_a_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t rate : 4,
lsig_reserved : 1,
length : 12,
parity : 1,
tail : 6,
pkt_type : 4,
captured_implicit_sounding : 1,
reserved : 2,
rx_integrity_check_passed : 1;
#else
uint32_t rx_integrity_check_passed : 1,
reserved : 2,
captured_implicit_sounding : 1,
pkt_type : 4,
tail : 6,
parity : 1,
length : 12,
lsig_reserved : 1,
rate : 4;
#endif
};
#define L_SIG_A_INFO_RATE_OFFSET 0x00000000
#define L_SIG_A_INFO_RATE_LSB 0
#define L_SIG_A_INFO_RATE_MSB 3
#define L_SIG_A_INFO_RATE_MASK 0x0000000f
#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000
#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4
#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4
#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010
#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000
#define L_SIG_A_INFO_LENGTH_LSB 5
#define L_SIG_A_INFO_LENGTH_MSB 16
#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0
#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000
#define L_SIG_A_INFO_PARITY_LSB 17
#define L_SIG_A_INFO_PARITY_MSB 17
#define L_SIG_A_INFO_PARITY_MASK 0x00020000
#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000
#define L_SIG_A_INFO_TAIL_LSB 18
#define L_SIG_A_INFO_TAIL_MSB 23
#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000
#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000
#define L_SIG_A_INFO_PKT_TYPE_LSB 24
#define L_SIG_A_INFO_PKT_TYPE_MSB 27
#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000
#define L_SIG_A_INFO_RESERVED_LSB 29
#define L_SIG_A_INFO_RESERVED_MSB 30
#define L_SIG_A_INFO_RESERVED_MASK 0x60000000
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _L_SIG_B_INFO_H_
#define _L_SIG_B_INFO_H_
#define NUM_OF_DWORDS_L_SIG_B_INFO 1
struct l_sig_b_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t rate : 4,
length : 12,
reserved : 15,
rx_integrity_check_passed : 1;
#else
uint32_t rx_integrity_check_passed : 1,
reserved : 15,
length : 12,
rate : 4;
#endif
};
#define L_SIG_B_INFO_RATE_OFFSET 0x00000000
#define L_SIG_B_INFO_RATE_LSB 0
#define L_SIG_B_INFO_RATE_MSB 3
#define L_SIG_B_INFO_RATE_MASK 0x0000000f
#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000
#define L_SIG_B_INFO_LENGTH_LSB 4
#define L_SIG_B_INFO_LENGTH_MSB 15
#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0
#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000
#define L_SIG_B_INFO_RESERVED_LSB 16
#define L_SIG_B_INFO_RESERVED_MSB 30
#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

31
hw/wcn8750/v1/macrx_abort_request_info.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACRX_ABORT_REQUEST_INFO_H_
#define _MACRX_ABORT_REQUEST_INFO_H_
#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
struct macrx_abort_request_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint16_t macrx_abort_reason : 8,
reserved_0 : 8;
#else
uint16_t reserved_0 : 8,
macrx_abort_reason : 8;
#endif
};
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00
#endif

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hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_
#define _MACTX_EHT_SIG_USR_MU_MIMO_H_
#include "eht_sig_usr_mu_mimo_info.h"
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2
#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1
struct mactx_eht_sig_usr_mu_mimo {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
#else
struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
#endif
};
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
#endif

87
hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_
#define _MACTX_EHT_SIG_USR_OFDMA_H_
#include "eht_sig_usr_ofdma_info.h"
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2
#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1
struct mactx_eht_sig_usr_ofdma {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
#else
struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
#endif
};
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
#endif

69
hw/wcn8750/v1/mactx_eht_sig_usr_su.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_EHT_SIG_USR_SU_H_
#define _MACTX_EHT_SIG_USR_SU_H_
#include "eht_sig_usr_su_info.h"
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2
#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1
struct mactx_eht_sig_usr_su {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
uint32_t tlv64_padding : 32;
#else
struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
uint32_t tlv64_padding : 32;
#endif
};
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000
#endif

132
hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_HE_SIG_A_MU_DL_H_
#define _MACTX_HE_SIG_A_MU_DL_H_
#include "he_sig_a_mu_dl_info.h"
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2
#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1
struct mactx_he_sig_a_mu_dl {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
#else
struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
#endif
};
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

82
hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h Normal file
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@ -0,0 +1,82 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_HE_SIG_A_MU_UL_H_
#define _MACTX_HE_SIG_A_MU_UL_H_
#include "he_sig_a_mu_ul_info.h"
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2
#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1
struct mactx_he_sig_a_mu_ul {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
#else
struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
#endif
};
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

157
hw/wcn8750/v1/mactx_he_sig_a_su.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_HE_SIG_A_SU_H_
#define _MACTX_HE_SIG_A_SU_H_
#include "he_sig_a_su_info.h"
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2
#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1
struct mactx_he_sig_a_su {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
#else
struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
#endif
};
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

44
hw/wcn8750/v1/mactx_he_sig_b1_mu.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_HE_SIG_B1_MU_H_
#define _MACTX_HE_SIG_B1_MU_H_
#include "he_sig_b1_mu_info.h"
#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2
#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1
struct mactx_he_sig_b1_mu {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
uint32_t tlv64_padding : 32;
#else
struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
uint32_t tlv64_padding : 32;
#endif
};
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000
#endif

77
hw/wcn8750/v1/mactx_he_sig_b2_mu.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_HE_SIG_B2_MU_H_
#define _MACTX_HE_SIG_B2_MU_H_
#include "he_sig_b2_mu_info.h"
#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2
#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1
struct mactx_he_sig_b2_mu {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
#else
struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
#endif
};
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
#endif

77
hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_HE_SIG_B2_OFDMA_H_
#define _MACTX_HE_SIG_B2_OFDMA_H_
#include "he_sig_b2_ofdma_info.h"
#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2
#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1
struct mactx_he_sig_b2_ofdma {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
#else
struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
#endif
};
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
#endif

102
hw/wcn8750/v1/mactx_ht_sig.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_HT_SIG_H_
#define _MACTX_HT_SIG_H_
#include "ht_sig_info.h"
#define NUM_OF_DWORDS_MACTX_HT_SIG 2
#define NUM_OF_QWORDS_MACTX_HT_SIG 1
struct mactx_ht_sig {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct ht_sig_info mactx_ht_sig_info_details;
#else
struct ht_sig_info mactx_ht_sig_info_details;
#endif
};
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

74
hw/wcn8750/v1/mactx_l_sig_a.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_L_SIG_A_H_
#define _MACTX_L_SIG_A_H_
#include "l_sig_a_info.h"
#define NUM_OF_DWORDS_MACTX_L_SIG_A 2
#define NUM_OF_QWORDS_MACTX_L_SIG_A 1
struct mactx_l_sig_a {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct l_sig_a_info mactx_l_sig_a_info_details;
uint32_t tlv64_padding : 32;
#else
struct l_sig_a_info mactx_l_sig_a_info_details;
uint32_t tlv64_padding : 32;
#endif
};
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000
#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32
#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63
#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000
#endif

49
hw/wcn8750/v1/mactx_l_sig_b.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_L_SIG_B_H_
#define _MACTX_L_SIG_B_H_
#include "l_sig_b_info.h"
#define NUM_OF_DWORDS_MACTX_L_SIG_B 2
#define NUM_OF_QWORDS_MACTX_L_SIG_B 1
struct mactx_l_sig_b {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct l_sig_b_info mactx_l_sig_b_info_details;
uint32_t tlv64_padding : 32;
#else
struct l_sig_b_info mactx_l_sig_b_info_details;
uint32_t tlv64_padding : 32;
#endif
};
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000
#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32
#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63
#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000
#endif

348
hw/wcn8750/v1/mactx_phy_desc.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_PHY_DESC_H_
#define _MACTX_PHY_DESC_H_
#define NUM_OF_DWORDS_MACTX_PHY_DESC 4
#define NUM_OF_QWORDS_MACTX_PHY_DESC 2
struct mactx_phy_desc {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t reserved_0a : 16,
bf_type : 2,
wait_sifs : 2,
dot11b_preamble_type : 1,
pkt_type : 4,
su_or_mu : 2,
mu_type : 1,
bandwidth : 3,
channel_capture : 1;
uint32_t mcs : 5,
global_ofdma_mimo_enable : 1,
stbc : 1,
dot11ax_su_extended : 1,
dot11ax_trigger_frame_embedded : 1,
tx_pwr_shared : 8,
tx_pwr_unshared : 8,
measure_power : 1,
tpc_glut_self_cal : 1,
back_to_back_transmission_expected : 1,
heavy_clip_nss : 3,
txbf_per_packet_no_csd_no_walsh : 1;
uint32_t ndp : 3,
ul_flag : 1,
triggered : 1,
ap_pkt_bw : 3,
ru_position_start : 8,
pcu_ppdu_setup_start_reason : 3,
tlv_source : 1,
reserved_2a : 1,
nss : 3,
stream_offset : 3,
reserved_2b : 2,
clpc_enable : 1,
mu_ndp : 1,
response_expected : 1;
uint32_t rx_chain_mask : 8,
rx_chain_mask_valid : 1,
ant_sel_valid : 1,
ant_sel : 1,
cp_setting : 2,
he_ppdu_subtype : 2,
active_channel : 3,
generate_phyrx_tx_start_timing : 1,
ltf_size : 2,
ru_size_updated_v2 : 4,
reserved_3c : 1,
u_sig_puncture_pattern_encoding : 6;
#else
uint32_t channel_capture : 1,
bandwidth : 3,
mu_type : 1,
su_or_mu : 2,
pkt_type : 4,
dot11b_preamble_type : 1,
wait_sifs : 2,
bf_type : 2,
reserved_0a : 16;
uint32_t txbf_per_packet_no_csd_no_walsh : 1,
heavy_clip_nss : 3,
back_to_back_transmission_expected : 1,
tpc_glut_self_cal : 1,
measure_power : 1,
tx_pwr_unshared : 8,
tx_pwr_shared : 8,
dot11ax_trigger_frame_embedded : 1,
dot11ax_su_extended : 1,
stbc : 1,
global_ofdma_mimo_enable : 1,
mcs : 5;
uint32_t response_expected : 1,
mu_ndp : 1,
clpc_enable : 1,
reserved_2b : 2,
stream_offset : 3,
nss : 3,
reserved_2a : 1,
tlv_source : 1,
pcu_ppdu_setup_start_reason : 3,
ru_position_start : 8,
ap_pkt_bw : 3,
triggered : 1,
ul_flag : 1,
ndp : 3;
uint32_t u_sig_puncture_pattern_encoding : 6,
reserved_3c : 1,
ru_size_updated_v2 : 4,
ltf_size : 2,
generate_phyrx_tx_start_timing : 1,
active_channel : 3,
he_ppdu_subtype : 2,
cp_setting : 2,
ant_sel : 1,
ant_sel_valid : 1,
rx_chain_mask_valid : 1,
rx_chain_mask : 8;
#endif
};
#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_RESERVED_0A_LSB 0
#define MACTX_PHY_DESC_RESERVED_0A_MSB 15
#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff
#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_BF_TYPE_LSB 16
#define MACTX_PHY_DESC_BF_TYPE_MSB 17
#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000
#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18
#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19
#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000
#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_PKT_TYPE_LSB 21
#define MACTX_PHY_DESC_PKT_TYPE_MSB 24
#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000
#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_SU_OR_MU_LSB 25
#define MACTX_PHY_DESC_SU_OR_MU_MSB 26
#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000
#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_MU_TYPE_LSB 27
#define MACTX_PHY_DESC_MU_TYPE_MSB 27
#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000
#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_BANDWIDTH_LSB 28
#define MACTX_PHY_DESC_BANDWIDTH_MSB 30
#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000
#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_MCS_LSB 32
#define MACTX_PHY_DESC_MCS_MSB 36
#define MACTX_PHY_DESC_MCS_MASK 0x0000001f00000000
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 37
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 37
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000002000000000
#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_STBC_LSB 38
#define MACTX_PHY_DESC_STBC_MSB 38
#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000
#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41
#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48
#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000
#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57
#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57
#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000
#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_NDP_LSB 0
#define MACTX_PHY_DESC_NDP_MSB 2
#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000007
#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_UL_FLAG_LSB 3
#define MACTX_PHY_DESC_UL_FLAG_MSB 3
#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000008
#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_TRIGGERED_LSB 4
#define MACTX_PHY_DESC_TRIGGERED_MSB 4
#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000010
#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_AP_PKT_BW_LSB 5
#define MACTX_PHY_DESC_AP_PKT_BW_MSB 7
#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000000000000e0
#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_RU_POSITION_START_LSB 8
#define MACTX_PHY_DESC_RU_POSITION_START_MSB 15
#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x000000000000ff00
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 16
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 18
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000070000
#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_TLV_SOURCE_LSB 19
#define MACTX_PHY_DESC_TLV_SOURCE_MSB 19
#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000080000
#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_RESERVED_2A_LSB 20
#define MACTX_PHY_DESC_RESERVED_2A_MSB 20
#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000100000
#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_NSS_LSB 21
#define MACTX_PHY_DESC_NSS_MSB 23
#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000
#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24
#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26
#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000
#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_RESERVED_2B_LSB 27
#define MACTX_PHY_DESC_RESERVED_2B_MSB 28
#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000
#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29
#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29
#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000
#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_MU_NDP_LSB 30
#define MACTX_PHY_DESC_MU_NDP_MSB 30
#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000
#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32
#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39
#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000
#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41
#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41
#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000
#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_ANT_SEL_LSB 42
#define MACTX_PHY_DESC_ANT_SEL_MSB 42
#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000
#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_CP_SETTING_LSB 43
#define MACTX_PHY_DESC_CP_SETTING_MSB 44
#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000
#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_LTF_SIZE_LSB 51
#define MACTX_PHY_DESC_LTF_SIZE_MSB 52
#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000
#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_RESERVED_3C_LSB 57
#define MACTX_PHY_DESC_RESERVED_3C_MSB 57
#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
#endif

122
hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_U_SIG_EHT_SU_MU_H_
#define _MACTX_U_SIG_EHT_SU_MU_H_
#include "u_sig_eht_su_mu_info.h"
#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2
#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1
struct mactx_u_sig_eht_su_mu {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
#else
struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
#endif
};
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

97
hw/wcn8750/v1/mactx_u_sig_eht_tb.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_U_SIG_EHT_TB_H_
#define _MACTX_U_SIG_EHT_TB_H_
#include "u_sig_eht_tb_info.h"
#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1
struct mactx_u_sig_eht_tb {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
#else
struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
#endif
};
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

482
hw/wcn8750/v1/mactx_user_desc_common.h Normal file
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@ -0,0 +1,482 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_USER_DESC_COMMON_H_
#define _MACTX_USER_DESC_COMMON_H_
#include "unallocated_ru_160_info.h"
#include "ru_allocation_160_info.h"
#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16
#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8
struct mactx_user_desc_common {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t num_users : 6,
reserved_0b : 5,
ltf_size : 2,
reserved_0c : 3,
he_stf_long : 1,
reserved_0d : 7,
num_users_he_sigb_band0 : 8;
uint32_t num_ltf_symbols : 3,
reserved_1a : 5,
num_users_he_sigb_band1 : 8,
reserved_1b : 16;
uint32_t packet_extension_a_factor : 2,
packet_extension_pe_disambiguity : 1,
packet_extension : 3,
reserved : 2,
he_sigb_dcm : 1,
reserved_2b : 7,
he_sigb_compression : 1,
reserved_2c : 15;
uint32_t he_sigb_0_mcs : 3,
reserved_3a : 13,
num_he_sigb_sym : 5,
center_ru_0 : 1,
center_ru_1 : 1,
reserved_3b : 1,
ftm_en : 1,
pe_nss : 3,
pe_ltf_size : 2,
pe_content : 1,
pe_chain_csd_en : 1;
struct ru_allocation_160_info ru_allocation_0123_details;
struct ru_allocation_160_info ru_allocation_4567_details;
struct unallocated_ru_160_info ru_allocation_160_0_details;
struct unallocated_ru_160_info ru_allocation_160_1_details;
uint32_t num_data_symbols : 16,
ndp_ru_tone_set_index : 7,
ndp_feedback_status : 1,
doppler_indication : 1,
reserved_14a : 7;
uint32_t spatial_reuse : 16,
distributed_ru : 1,
dru_spreading_bw : 2,
reserved_15a : 13;
#else
uint32_t num_users_he_sigb_band0 : 8,
reserved_0d : 7,
he_stf_long : 1,
reserved_0c : 3,
ltf_size : 2,
reserved_0b : 5,
num_users : 6;
uint32_t reserved_1b : 16,
num_users_he_sigb_band1 : 8,
reserved_1a : 5,
num_ltf_symbols : 3;
uint32_t reserved_2c : 15,
he_sigb_compression : 1,
reserved_2b : 7,
he_sigb_dcm : 1,
reserved : 2,
packet_extension : 3,
packet_extension_pe_disambiguity : 1,
packet_extension_a_factor : 2;
uint32_t pe_chain_csd_en : 1,
pe_content : 1,
pe_ltf_size : 2,
pe_nss : 3,
ftm_en : 1,
reserved_3b : 1,
center_ru_1 : 1,
center_ru_0 : 1,
num_he_sigb_sym : 5,
reserved_3a : 13,
he_sigb_0_mcs : 3;
struct ru_allocation_160_info ru_allocation_0123_details;
struct ru_allocation_160_info ru_allocation_4567_details;
struct unallocated_ru_160_info ru_allocation_160_0_details;
struct unallocated_ru_160_info ru_allocation_160_1_details;
uint32_t reserved_14a : 7,
doppler_indication : 1,
ndp_feedback_status : 1,
ndp_ru_tone_set_index : 7,
num_data_symbols : 16;
uint32_t reserved_15a : 13,
dru_spreading_bw : 2,
distributed_ru : 1,
spatial_reuse : 16;
#endif
};
#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0
#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5
#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f
#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6
#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10
#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0
#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11
#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12
#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800
#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13
#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15
#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000
#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17
#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23
#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000
#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35
#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39
#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000
#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48
#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63
#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038
#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6
#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7
#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100
#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9
#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15
#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000
#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17
#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31
#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000
#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35
#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47
#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000
#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55
#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55
#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000
#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56
#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56
#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000
#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57
#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59
#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000
#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62
#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62
#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000
#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038
#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25
#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31
#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000
#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET 0x0000000000000038
#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB 48
#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB 48
#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK 0x0001000000000000
#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET 0x0000000000000038
#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB 49
#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB 50
#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK 0x0006000000000000
#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038
#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 51
#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63
#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xfff8000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_USER_DESC_PER_USER_H_
#define _MACTX_USER_DESC_PER_USER_H_
#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6
#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3
struct mactx_user_desc_per_user {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t psdu_length : 24,
reserved_0a : 8;
uint32_t ru_start_index : 8,
ru_size : 4,
reserved_1b : 4,
ofdma_mu_mimo_enabled : 1,
nss : 3,
stream_offset : 3,
reserved_1c : 1,
mcs : 5,
dcm : 1,
reserved_1d : 2;
uint32_t fec_type : 1,
reserved_2a : 1,
qam_diff1 : 2,
qam_diff2 : 2,
qam_diff3 : 2,
user_bf_type : 2,
a_factor_ldpc2x : 2,
extra_sym_ldpc2x : 1,
cw_len_2x : 2,
reserved_2b : 1,
drop_user_cbf : 1,
a_factor_ldpc1x : 2,
extra_sym_ldpc1x : 1,
cw_len_1x : 2,
ldpc1x_used : 1,
ldpc2x_used : 1,
ldpc_extra_symbol : 1,
force_extra_symbol : 1,
ldpc_2x_codeword : 1,
reserved_2d : 5;
uint32_t sw_peer_id : 16,
per_user_subband_mask : 16;
uint32_t ldpc_num_avbits : 27,
reserved_4a : 5;
uint32_t num_cw_1x : 16,
num_cw_2x : 16;
#else
uint32_t reserved_0a : 8,
psdu_length : 24;
uint32_t reserved_1d : 2,
dcm : 1,
mcs : 5,
reserved_1c : 1,
stream_offset : 3,
nss : 3,
ofdma_mu_mimo_enabled : 1,
reserved_1b : 4,
ru_size : 4,
ru_start_index : 8;
uint32_t reserved_2d : 5,
ldpc_2x_codeword : 1,
force_extra_symbol : 1,
ldpc_extra_symbol : 1,
ldpc2x_used : 1,
ldpc1x_used : 1,
cw_len_1x : 2,
extra_sym_ldpc1x : 1,
a_factor_ldpc1x : 2,
drop_user_cbf : 1,
reserved_2b : 1,
cw_len_2x : 2,
extra_sym_ldpc2x : 1,
a_factor_ldpc2x : 2,
user_bf_type : 2,
qam_diff3 : 2,
qam_diff2 : 2,
qam_diff1 : 2,
reserved_2a : 1,
fec_type : 1;
uint32_t per_user_subband_mask : 16,
sw_peer_id : 16;
uint32_t reserved_4a : 5,
ldpc_num_avbits : 27;
uint32_t num_cw_2x : 16,
num_cw_1x : 16;
#endif
};
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000
#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40
#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43
#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000
#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_NSS_LSB 49
#define MACTX_USER_DESC_PER_USER_NSS_MSB 51
#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000
#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_MCS_LSB 56
#define MACTX_USER_DESC_PER_USER_MCS_MSB 60
#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x1f00000000000000
#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_DCM_LSB 61
#define MACTX_USER_DESC_PER_USER_DCM_MSB 61
#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x2000000000000000
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 62
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xc000000000000000
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 1
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x0000000000000002
#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB 2
#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB 3
#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK 0x000000000000000c
#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB 4
#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB 5
#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK 0x0000000000000030
#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB 6
#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB 7
#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK 0x00000000000000c0
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300
#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB 10
#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB 11
#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK 0x0000000000000c00
#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB 12
#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB 12
#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK 0x0000000000001000
#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB 13
#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB 14
#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK 0x0000000000006000
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 15
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000000000008000
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000
#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB 17
#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB 18
#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK 0x0000000000060000
#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB 19
#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB 19
#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK 0x0000000000080000
#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB 20
#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB 21
#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK 0x0000000000300000
#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB 22
#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB 22
#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK 0x0000000000400000
#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB 23
#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB 23
#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK 0x0000000000800000
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000
#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB 26
#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB 26
#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK 0x0000000004000000
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 27
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000f8000000
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000
#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB 0
#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB 26
#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK 0x0000000007ffffff
#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB 27
#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB 31
#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK 0x00000000f8000000
#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB 32
#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB 47
#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK 0x0000ffff00000000
#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET 0x0000000000000010
#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB 48
#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB 63
#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK 0xffff000000000000
#endif

112
hw/wcn8750/v1/mactx_vht_sig_a.h Normal file
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@ -0,0 +1,112 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_VHT_SIG_A_H_
#define _MACTX_VHT_SIG_A_H_
#include "vht_sig_a_info.h"
#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2
#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1
struct mactx_vht_sig_a {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_a_info mactx_vht_sig_a_info_details;
#else
struct vht_sig_a_info mactx_vht_sig_a_info_details;
#endif
};
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

182
hw/wcn8750/v1/mactx_vht_sig_b_mu160.h Normal file
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@ -0,0 +1,182 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_VHT_SIG_B_MU160_H_
#define _MACTX_VHT_SIG_B_MU160_H_
#include "vht_sig_b_mu160_info.h"
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4
struct mactx_vht_sig_b_mu160 {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
#else
struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
#endif
};
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000
#endif

54
hw/wcn8750/v1/mactx_vht_sig_b_mu20.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_VHT_SIG_B_MU20_H_
#define _MACTX_VHT_SIG_B_MU20_H_
#include "vht_sig_b_mu20_info.h"
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1
struct mactx_vht_sig_b_mu20 {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
uint32_t tlv64_padding : 32;
#else
struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
uint32_t tlv64_padding : 32;
#endif
};
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000
#endif

67
hw/wcn8750/v1/mactx_vht_sig_b_mu40.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_VHT_SIG_B_MU40_H_
#define _MACTX_VHT_SIG_B_MU40_H_
#include "vht_sig_b_mu40_info.h"
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1
struct mactx_vht_sig_b_mu40 {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
#else
struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
#endif
};
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000
#endif

102
hw/wcn8750/v1/mactx_vht_sig_b_mu80.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_VHT_SIG_B_MU80_H_
#define _MACTX_VHT_SIG_B_MU80_H_
#include "vht_sig_b_mu80_info.h"
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2
struct mactx_vht_sig_b_mu80 {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
#else
struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
#endif
};
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000
#endif

222
hw/wcn8750/v1/mactx_vht_sig_b_su160.h Normal file
View file

@ -0,0 +1,222 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_VHT_SIG_B_SU160_H_
#define _MACTX_VHT_SIG_B_SU160_H_
#include "vht_sig_b_su160_info.h"
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4
struct mactx_vht_sig_b_su160 {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
#else
struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
#endif
};
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000
#endif

54
hw/wcn8750/v1/mactx_vht_sig_b_su20.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_VHT_SIG_B_SU20_H_
#define _MACTX_VHT_SIG_B_SU20_H_
#include "vht_sig_b_su20_info.h"
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1
struct mactx_vht_sig_b_su20 {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
uint32_t tlv64_padding : 32;
#else
struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
uint32_t tlv64_padding : 32;
#endif
};
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000
#endif

72
hw/wcn8750/v1/mactx_vht_sig_b_su40.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_VHT_SIG_B_SU40_H_
#define _MACTX_VHT_SIG_B_SU40_H_
#include "vht_sig_b_su40_info.h"
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1
struct mactx_vht_sig_b_su40 {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
#else
struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
#endif
};
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000
#endif

122
hw/wcn8750/v1/mactx_vht_sig_b_su80.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MACTX_VHT_SIG_B_SU80_H_
#define _MACTX_VHT_SIG_B_SU80_H_
#include "vht_sig_b_su80_info.h"
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2
struct mactx_vht_sig_b_su80 {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
#else
struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
#endif
};
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000
#endif

52
hw/wcn8750/v1/mlo_sta_id_details.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MLO_STA_ID_DETAILS_H_
#define _MLO_STA_ID_DETAILS_H_
#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1
struct mlo_sta_id_details {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint16_t nstr_mlo_sta_id : 10,
block_self_ml_sync : 1,
block_partner_ml_sync : 1,
nstr_mlo_sta_id_valid : 1,
reserved_0a : 3;
#else
uint16_t reserved_0a : 3,
nstr_mlo_sta_id_valid : 1,
block_partner_ml_sync : 1,
block_self_ml_sync : 1,
nstr_mlo_sta_id : 10;
#endif
};
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000
#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13
#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15
#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MON_BUFFER_ADDR_H_
#define _MON_BUFFER_ADDR_H_
#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4
#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2
struct mon_buffer_addr {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
uint32_t dma_length : 12,
reserved_2a : 4,
msdu_continuation : 1,
truncated : 1,
reserved_2b : 14;
uint32_t tlv64_padding : 32;
#else
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
uint32_t reserved_2b : 14,
truncated : 1,
msdu_continuation : 1,
reserved_2a : 4,
dma_length : 12;
uint32_t tlv64_padding : 32;
#endif
};
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000
#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008
#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0
#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11
#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff
#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008
#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12
#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15
#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000
#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008
#define MON_BUFFER_ADDR_TRUNCATED_LSB 17
#define MON_BUFFER_ADDR_TRUNCATED_MSB 17
#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000
#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008
#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18
#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31
#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000
#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008
#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32
#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63
#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MON_DESTINATION_RING_H_
#define _MON_DESTINATION_RING_H_
#define NUM_OF_DWORDS_MON_DESTINATION_RING 4
struct mon_destination_ring {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t stat_buf_virt_addr_31_0 : 32;
uint32_t stat_buf_virt_addr_63_32 : 32;
uint32_t ppdu_id : 32;
uint32_t end_offset : 12,
reserved_3a : 2,
link_info : 2,
end_reason : 2,
initiator : 1,
empty_descriptor : 1,
pkt_buffer_cnt : 8,
looping_count : 4;
#else
uint32_t stat_buf_virt_addr_31_0 : 32;
uint32_t stat_buf_virt_addr_63_32 : 32;
uint32_t ppdu_id : 32;
uint32_t looping_count : 4,
pkt_buffer_cnt : 8,
empty_descriptor : 1,
initiator : 1,
end_reason : 2,
link_info : 2,
reserved_3a : 2,
end_offset : 12;
#endif
};
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff
#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008
#define MON_DESTINATION_RING_PPDU_ID_LSB 0
#define MON_DESTINATION_RING_PPDU_ID_MSB 31
#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff
#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c
#define MON_DESTINATION_RING_END_OFFSET_LSB 0
#define MON_DESTINATION_RING_END_OFFSET_MSB 11
#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff
#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c
#define MON_DESTINATION_RING_RESERVED_3A_LSB 12
#define MON_DESTINATION_RING_RESERVED_3A_MSB 13
#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000
#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c
#define MON_DESTINATION_RING_LINK_INFO_LSB 14
#define MON_DESTINATION_RING_LINK_INFO_MSB 15
#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000
#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c
#define MON_DESTINATION_RING_END_REASON_LSB 16
#define MON_DESTINATION_RING_END_REASON_MSB 17
#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000
#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c
#define MON_DESTINATION_RING_INITIATOR_LSB 18
#define MON_DESTINATION_RING_INITIATOR_MSB 18
#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000
#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET 0x0000000c
#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB 20
#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB 27
#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK 0x0ff00000
#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c
#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28
#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31
#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MON_DROP_H_
#define _MON_DROP_H_
#define NUM_OF_DWORDS_MON_DROP 2
#define NUM_OF_QWORDS_MON_DROP 1
struct mon_drop {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t ppdu_id : 32;
uint32_t ppdu_drop_cnt : 10,
mpdu_drop_cnt : 10,
tlv_drop_cnt : 10,
end_of_ppdu_seen : 1,
reserved_1a : 1;
#else
uint32_t ppdu_id : 32;
uint32_t reserved_1a : 1,
end_of_ppdu_seen : 1,
tlv_drop_cnt : 10,
mpdu_drop_cnt : 10,
ppdu_drop_cnt : 10;
#endif
};
#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000
#define MON_DROP_PPDU_ID_LSB 0
#define MON_DROP_PPDU_ID_MSB 31
#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff
#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000
#define MON_DROP_PPDU_DROP_CNT_LSB 32
#define MON_DROP_PPDU_DROP_CNT_MSB 41
#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000
#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000
#define MON_DROP_MPDU_DROP_CNT_LSB 42
#define MON_DROP_MPDU_DROP_CNT_MSB 51
#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000
#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000
#define MON_DROP_TLV_DROP_CNT_LSB 52
#define MON_DROP_TLV_DROP_CNT_MSB 61
#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000
#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000
#define MON_DROP_END_OF_PPDU_SEEN_LSB 62
#define MON_DROP_END_OF_PPDU_SEEN_MSB 62
#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000
#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000
#define MON_DROP_RESERVED_1A_LSB 63
#define MON_DROP_RESERVED_1A_MSB 63
#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000
#endif

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hw/wcn8750/v1/mon_ingress_ring.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _MON_INGRESS_RING_H_
#define _MON_INGRESS_RING_H_
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_MON_INGRESS_RING 4
struct mon_ingress_ring {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct buffer_addr_info buffer_addr_info_details;
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
#else
struct buffer_addr_info buffer_addr_info_details;
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
#endif
};
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef MSMHWIOBASE_H
#define MSMHWIOBASE_H
#define HOST_WCSS_WCSS_BASE 0x0
#define HOST_WCSS_WCSS_BASE_SIZE 0x00d00000
#define HOST_WCSS_WCSS_BASE_PHYS 0x00000000
#define HOST_HZ_AUXSSAUXSS_SWI_BASE 0x1900000
#define HOST_HZ_AUXSSAUXSS_SWI_BASE_SIZE 0x00007000
#define HOST_HZ_AUXSSAUXSS_SWI_BASE_PHYS 0x01900000
#define HOST_WLAN_HZ_ZEALIS_AON_BASE 0x1907000
#define HOST_WLAN_HZ_ZEALIS_AON_BASE_SIZE 0x00019000
#define HOST_WLAN_HZ_ZEALIS_AON_BASE_PHYS 0x01907000
#define HOST_TLMM_BASE 0x1a00000
#define HOST_TLMM_BASE_SIZE 0x00100000
#define HOST_TLMM_BASE_PHYS 0x01a00000
#define HOST_CORE_TOP_CSR_BASE 0x1b00000
#define HOST_CORE_TOP_CSR_BASE_SIZE 0x0003f000
#define HOST_CORE_TOP_CSR_BASE_PHYS 0x01b00000
#define QUPV3_QUPV3_ID_3_BASE 0x1b40000
#define QUPV3_QUPV3_ID_3_BASE_SIZE 0x00040000
#define QUPV3_QUPV3_ID_3_BASE_PHYS 0x01b40000
#define HOST_SOC_WFSS_CE_REG_BASE 0x1b80000
#define HOST_SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000
#define HOST_SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000
#define HOST_WL_TLMM_BASE 0x1bc0000
#define HOST_WL_TLMM_BASE_SIZE 0x00020000
#define HOST_WL_TLMM_BASE_PHYS 0x01bc0000
#define HOST_TSENS_SROT_BASE 0x1bf0000
#define HOST_TSENS_SROT_BASE_SIZE 0x00001000
#define HOST_TSENS_SROT_BASE_PHYS 0x01bf0000
#define HOST_TSENS_TM_BASE 0x1bf1000
#define HOST_TSENS_TM_BASE_SIZE 0x00001000
#define HOST_TSENS_TM_BASE_PHYS 0x01bf1000
#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE 0x1c00000
#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE_SIZE 0x00080000
#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE_PHYS 0x01c00000
#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE 0x1c80000
#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE_SIZE 0x0007fffd
#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE_PHYS 0x01c80000
#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE 0x1d00000
#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE_SIZE 0x00100000
#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE_PHYS 0x01d00000
#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE 0x1e00000
#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000
#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000
#define HOST_SECURITY_CONTROL_WLAN_BASE 0x1e20000
#define HOST_SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000
#define HOST_SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000
#define HOST_EDPD_CAL_ACC_BASE 0x1e28000
#define HOST_EDPD_CAL_ACC_BASE_SIZE 0x00003000
#define HOST_EDPD_CAL_ACC_BASE_PHYS 0x01e28000
#define HOST_CPR_CX_CPR3_BASE 0x1e30000
#define HOST_CPR_CX_CPR3_BASE_SIZE 0x00004000
#define HOST_CPR_CX_CPR3_BASE_PHYS 0x01e30000
#define HOST_CPR_MX_CPR3_BASE 0x1e34000
#define HOST_CPR_MX_CPR3_BASE_SIZE 0x00004000
#define HOST_CPR_MX_CPR3_BASE_PHYS 0x01e34000
#define HOST_WCSS_IE_BASE 0x1e38000
#define HOST_WCSS_IE_BASE_SIZE 0x00001000
#define HOST_WCSS_IE_BASE_PHYS 0x01e38000
#define HOST_GCC_GCC_BASE 0x1e40000
#define HOST_GCC_GCC_BASE_SIZE 0x0000048c
#define HOST_GCC_GCC_BASE_PHYS 0x01e40000
#define HOST_PCNOC_0_BUS_TIMEOUT_BASE 0x1e60000
#define HOST_PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define HOST_PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000
#define HOST_PCNOC_1_BUS_TIMEOUT_BASE 0x1e61000
#define HOST_PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define HOST_PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000
#define HOST_PCNOC_2_BUS_TIMEOUT_BASE 0x1e62000
#define HOST_PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define HOST_PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000
#define HOST_PCNOC_3_BUS_TIMEOUT_BASE 0x1e63000
#define HOST_PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define HOST_PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000
#define HOST_PCNOC_4_BUS_TIMEOUT_BASE 0x1e64000
#define HOST_PCNOC_4_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define HOST_PCNOC_4_BUS_TIMEOUT_BASE_PHYS 0x01e64000
#define HOST_PCNOC_5_BUS_TIMEOUT_BASE 0x1e65000
#define HOST_PCNOC_5_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define HOST_PCNOC_5_BUS_TIMEOUT_BASE_PHYS 0x01e65000
#define HOST_RRI_PREFETCH_REG_BASE 0x1e70000
#define HOST_RRI_PREFETCH_REG_BASE_SIZE 0x00010000
#define HOST_RRI_PREFETCH_REG_BASE_PHYS 0x01e70000
#define HOST_SYSTEM_NOC_BASE 0x1e80000
#define HOST_SYSTEM_NOC_BASE_SIZE 0x0000a000
#define HOST_SYSTEM_NOC_BASE_PHYS 0x01e80000
#define HOST_PC_NOC_BASE 0x1f00000
#define HOST_PC_NOC_BASE_SIZE 0x00003880
#define HOST_PC_NOC_BASE_PHYS 0x01f00000
#define HOST_WLAON_WL_AON_REG_BASE 0x1f80000
#define HOST_WLAON_WL_AON_REG_BASE_SIZE 0x000007f0
#define HOST_WLAON_WL_AON_REG_BASE_PHYS 0x01f80000
#define HOST_SYSPM_SYSPM_REG_BASE 0x1f82000
#define HOST_SYSPM_SYSPM_REG_BASE_SIZE 0x00001000
#define HOST_SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000
#define HOST_PMU_WLAN_PMU_TOP_BASE 0x1f88000
#define HOST_PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000400
#define HOST_PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000
#define HOST_PMU_NOC_BASE 0x1f8a000
#define HOST_PMU_NOC_BASE_SIZE 0x00000180
#define HOST_PMU_NOC_BASE_PHYS 0x01f8a000
#define HOST_BOOT_ROM 0x1200000
#define HOST_BOOT_ROM_SIZE 0x00004800
#define HOST_BOOT_ROM_PHYS 0x01200000
#define HOST_SYSTEM_IRAM 0x1400000
#define HOST_SYSTEM_IRAM_SIZE 0x00020000
#define HOST_SYSTEM_IRAM_PHYS 0x01400000
#define HOST_ZEALIS_SRAM 0x28c0000
#define HOST_ZEALIS_SRAM_SIZE 0x00040000
#define HOST_ZEALIS_SRAM_PHYS 0x028c0000
#define HOST_PCIE_ATU_REGION 0x4000000
#define HOST_PCIE_ATU_REGION_SIZE 0x40000000
#define HOST_PCIE_ATU_REGION_PHYS 0x04000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef __MSMHWIOREG_H__
#define __MSMHWIOREG_H__
#include "msmhwiobase.h"
#define HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00001000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x408)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8
#define HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00000000)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \
in_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x4)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \
in_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8
#define HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00003000)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
in_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x4)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
in_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x400)
#define HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00002000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
in_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x4)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
in_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x400)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x58)
#endif

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hw/wcn8750/v1/no_ack_report.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _NO_ACK_REPORT_H_
#define _NO_ACK_REPORT_H_
#define NUM_OF_DWORDS_NO_ACK_REPORT 4
struct no_ack_report {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t no_ack_transmit_reason : 4,
macrx_abort_reason : 4,
phyrx_abort_reason : 8,
frame_control : 16;
uint32_t rx_ppdu_duration : 24,
sr_ppdu_during_obss : 1,
selfgen_response_reason_to_sr_ppdu : 4,
reserved_1 : 3;
uint32_t pre_bt_broadcast_status_details : 12,
first_bt_broadcast_status_details : 12,
reserved_2 : 8;
uint32_t second_bt_broadcast_status_details : 12,
reserved_3 : 20;
#else
uint32_t frame_control : 16,
phyrx_abort_reason : 8,
macrx_abort_reason : 4,
no_ack_transmit_reason : 4;
uint32_t reserved_1 : 3,
selfgen_response_reason_to_sr_ppdu : 4,
sr_ppdu_during_obss : 1,
rx_ppdu_duration : 24;
uint32_t reserved_2 : 8,
first_bt_broadcast_status_details : 12,
pre_bt_broadcast_status_details : 12;
uint32_t reserved_3 : 20,
second_bt_broadcast_status_details : 12;
#endif
};
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f
#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000
#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00
#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16
#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31
#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004
#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0
#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23
#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000
#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004
#define NO_ACK_REPORT_RESERVED_1_LSB 29
#define NO_ACK_REPORT_RESERVED_1_MSB 31
#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000
#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008
#define NO_ACK_REPORT_RESERVED_2_LSB 24
#define NO_ACK_REPORT_RESERVED_2_MSB 31
#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c
#define NO_ACK_REPORT_RESERVED_3_LSB 12
#define NO_ACK_REPORT_RESERVED_3_MSB 31
#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000
#endif

944
hw/wcn8750/v1/ofdma_trigger_details.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _OFDMA_TRIGGER_DETAILS_H_
#define _OFDMA_TRIGGER_DETAILS_H_
#include "mlo_sta_id_details.h"
#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26
#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13
struct ofdma_trigger_details {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t ax_trigger_source : 1,
rx_trigger_frame_user_source : 2,
received_bandwidth : 3,
txop_duration_all_ones : 1,
eht_trigger_response : 1,
pre_rssi_comb : 8,
rssi_comb : 8,
rxpcu_pcie_l0_req_duration : 8;
uint32_t he_trigger_ul_ppdu_length : 5,
he_trigger_ru_allocation : 8,
he_trigger_dl_tx_power : 5,
he_trigger_ul_target_rssi : 5,
he_trigger_ul_mcs : 2,
he_trigger_reserved : 1,
bss_color : 6;
uint32_t trigger_type : 4,
lsig_response_length : 12,
cascade_indication : 1,
carrier_sense : 1,
bandwidth : 2,
cp_ltf_size : 2,
mu_mimo_ltf_mode : 1,
number_of_ltfs : 3,
stbc : 1,
ldpc_extra_symbol : 1,
ap_tx_power_lsb_part : 4;
uint32_t ap_tx_power_msb_part : 2,
packet_extension_a_factor : 2,
packet_extension_pe_disambiguity : 1,
spatial_reuse : 16,
doppler : 1,
he_siga_reserved : 9,
reserved_3b : 1;
uint32_t aid12 : 12,
ru_allocation : 9,
mcs : 4,
dcm : 1,
start_spatial_stream : 3,
number_of_spatial_stream : 3;
uint32_t target_rssi : 7,
coding_type : 1,
mpdu_mu_spacing_factor : 2,
tid_aggregation_limit : 3,
reserved_5b : 1,
prefered_ac : 2,
bar_control_ack_policy : 1,
bar_control_multi_tid : 1,
bar_control_compressed_bitmap : 1,
bar_control_reserved : 9,
bar_control_tid_info : 4;
uint32_t nr0_per_tid_info_reserved : 12,
nr0_per_tid_info_tid_value : 4,
nr0_start_seq_ctrl_frag_number : 4,
nr0_start_seq_ctrl_start_seq_number : 12;
uint32_t nr1_per_tid_info_reserved : 12,
nr1_per_tid_info_tid_value : 4,
nr1_start_seq_ctrl_frag_number : 4,
nr1_start_seq_ctrl_start_seq_number : 12;
uint32_t nr2_per_tid_info_reserved : 12,
nr2_per_tid_info_tid_value : 4,
nr2_start_seq_ctrl_frag_number : 4,
nr2_start_seq_ctrl_start_seq_number : 12;
uint32_t nr3_per_tid_info_reserved : 12,
nr3_per_tid_info_tid_value : 4,
nr3_start_seq_ctrl_frag_number : 4,
nr3_start_seq_ctrl_start_seq_number : 12;
uint32_t nr4_per_tid_info_reserved : 12,
nr4_per_tid_info_tid_value : 4,
nr4_start_seq_ctrl_frag_number : 4,
nr4_start_seq_ctrl_start_seq_number : 12;
uint32_t nr5_per_tid_info_reserved : 12,
nr5_per_tid_info_tid_value : 4,
nr5_start_seq_ctrl_frag_number : 4,
nr5_start_seq_ctrl_start_seq_number : 12;
uint32_t nr6_per_tid_info_reserved : 12,
nr6_per_tid_info_tid_value : 4,
nr6_start_seq_ctrl_frag_number : 4,
nr6_start_seq_ctrl_start_seq_number : 12;
uint32_t nr7_per_tid_info_reserved : 12,
nr7_per_tid_info_tid_value : 4,
nr7_start_seq_ctrl_frag_number : 4,
nr7_start_seq_ctrl_start_seq_number : 12;
uint32_t fb_segment_retransmission_bitmap : 8,
reserved_14a : 2,
u_sig_puncture_pattern_encoding : 6,
dot11be_puncture_bitmap : 16;
uint32_t rx_chain_mask : 8,
rx_duration_field : 16,
scrambler_seed : 7,
rx_chain_mask_type : 1;
struct mlo_sta_id_details mlo_sta_id_details_rx;
uint16_t normalized_pre_rssi_comb : 8,
normalized_rssi_comb : 8;
uint32_t sw_peer_id : 16,
response_tx_duration : 16;
uint32_t __reserved_g_0005_trigger_subtype : 4,
tbr_trigger_common_info_79_68 : 12,
tbr_trigger_sound_reserved_20_12 : 9,
i2r_rep : 3,
tbr_trigger_sound_reserved_25_24 : 2,
reserved_18a : 1,
qos_null_only_response_tx : 1;
uint32_t tbr_trigger_sound_sac : 16,
reserved_19a : 8,
u_sig_reserved2 : 5,
reserved_19b : 3;
uint32_t eht_special_aid12 : 12,
phy_version : 3,
bandwidth_ext : 2,
eht_spatial_reuse : 8,
u_sig_reserved1 : 7;
uint32_t eht_trigger_special_user_info_71_40 : 32;
uint32_t __reserved_g_0086 : 1,
__reserved_g_0074 : 4,
blackout_details_en : 1,
uhr_trig_response : 1,
mcs_ext : 1,
dso_primary20_index_select : 4,
dso_icf_reception : 1,
dru_spreading_bw : 2,
dru_indication_per_80mhz : 4,
coding_type_ext : 1,
pad_duration : 5,
ects_as_tb_ppdu : 1,
reserved_22a : 6;
uint32_t dso_cca_puncture_pattern : 16,
dso_freq_subband_channel_bonding_mask : 16;
uint32_t __reserved_g_0034 : 1,
enable_steering : 1,
q2q_mba : 1,
reserved_24a : 29;
uint32_t reserved_25a : 32;
#else
uint32_t rxpcu_pcie_l0_req_duration : 8,
rssi_comb : 8,
pre_rssi_comb : 8,
eht_trigger_response : 1,
txop_duration_all_ones : 1,
received_bandwidth : 3,
rx_trigger_frame_user_source : 2,
ax_trigger_source : 1;
uint32_t bss_color : 6,
he_trigger_reserved : 1,
he_trigger_ul_mcs : 2,
he_trigger_ul_target_rssi : 5,
he_trigger_dl_tx_power : 5,
he_trigger_ru_allocation : 8,
he_trigger_ul_ppdu_length : 5;
uint32_t ap_tx_power_lsb_part : 4,
ldpc_extra_symbol : 1,
stbc : 1,
number_of_ltfs : 3,
mu_mimo_ltf_mode : 1,
cp_ltf_size : 2,
bandwidth : 2,
carrier_sense : 1,
cascade_indication : 1,
lsig_response_length : 12,
trigger_type : 4;
uint32_t reserved_3b : 1,
he_siga_reserved : 9,
doppler : 1,
spatial_reuse : 16,
packet_extension_pe_disambiguity : 1,
packet_extension_a_factor : 2,
ap_tx_power_msb_part : 2;
uint32_t number_of_spatial_stream : 3,
start_spatial_stream : 3,
dcm : 1,
mcs : 4,
ru_allocation : 9,
aid12 : 12;
uint32_t bar_control_tid_info : 4,
bar_control_reserved : 9,
bar_control_compressed_bitmap : 1,
bar_control_multi_tid : 1,
bar_control_ack_policy : 1,
prefered_ac : 2,
reserved_5b : 1,
tid_aggregation_limit : 3,
mpdu_mu_spacing_factor : 2,
coding_type : 1,
target_rssi : 7;
uint32_t nr0_start_seq_ctrl_start_seq_number : 12,
nr0_start_seq_ctrl_frag_number : 4,
nr0_per_tid_info_tid_value : 4,
nr0_per_tid_info_reserved : 12;
uint32_t nr1_start_seq_ctrl_start_seq_number : 12,
nr1_start_seq_ctrl_frag_number : 4,
nr1_per_tid_info_tid_value : 4,
nr1_per_tid_info_reserved : 12;
uint32_t nr2_start_seq_ctrl_start_seq_number : 12,
nr2_start_seq_ctrl_frag_number : 4,
nr2_per_tid_info_tid_value : 4,
nr2_per_tid_info_reserved : 12;
uint32_t nr3_start_seq_ctrl_start_seq_number : 12,
nr3_start_seq_ctrl_frag_number : 4,
nr3_per_tid_info_tid_value : 4,
nr3_per_tid_info_reserved : 12;
uint32_t nr4_start_seq_ctrl_start_seq_number : 12,
nr4_start_seq_ctrl_frag_number : 4,
nr4_per_tid_info_tid_value : 4,
nr4_per_tid_info_reserved : 12;
uint32_t nr5_start_seq_ctrl_start_seq_number : 12,
nr5_start_seq_ctrl_frag_number : 4,
nr5_per_tid_info_tid_value : 4,
nr5_per_tid_info_reserved : 12;
uint32_t nr6_start_seq_ctrl_start_seq_number : 12,
nr6_start_seq_ctrl_frag_number : 4,
nr6_per_tid_info_tid_value : 4,
nr6_per_tid_info_reserved : 12;
uint32_t nr7_start_seq_ctrl_start_seq_number : 12,
nr7_start_seq_ctrl_frag_number : 4,
nr7_per_tid_info_tid_value : 4,
nr7_per_tid_info_reserved : 12;
uint32_t dot11be_puncture_bitmap : 16,
u_sig_puncture_pattern_encoding : 6,
reserved_14a : 2,
fb_segment_retransmission_bitmap : 8;
uint32_t rx_chain_mask_type : 1,
scrambler_seed : 7,
rx_duration_field : 16,
rx_chain_mask : 8;
uint32_t normalized_rssi_comb : 8,
normalized_pre_rssi_comb : 8;
struct mlo_sta_id_details mlo_sta_id_details_rx;
uint32_t response_tx_duration : 16,
sw_peer_id : 16;
uint32_t qos_null_only_response_tx : 1,
reserved_18a : 1,
tbr_trigger_sound_reserved_25_24 : 2,
i2r_rep : 3,
tbr_trigger_sound_reserved_20_12 : 9,
tbr_trigger_common_info_79_68 : 12,
__reserved_g_0005_trigger_subtype : 4;
uint32_t reserved_19b : 3,
u_sig_reserved2 : 5,
reserved_19a : 8,
tbr_trigger_sound_sac : 16;
uint32_t u_sig_reserved1 : 7,
eht_spatial_reuse : 8,
bandwidth_ext : 2,
phy_version : 3,
eht_special_aid12 : 12;
uint32_t eht_trigger_special_user_info_71_40 : 32;
uint32_t reserved_22a : 6,
ects_as_tb_ppdu : 1,
pad_duration : 5,
coding_type_ext : 1,
dru_indication_per_80mhz : 4,
dru_spreading_bw : 2,
dso_icf_reception : 1,
dso_primary20_index_select : 4,
mcs_ext : 1,
uhr_trig_response : 1,
blackout_details_en : 1,
__reserved_g_0074 : 4,
__reserved_g_0086 : 1;
uint32_t dso_freq_subband_channel_bonding_mask : 16,
dso_cca_puncture_pattern : 16;
uint32_t reserved_24a : 29,
q2q_mba : 1,
enable_steering : 1,
__reserved_g_0034 : 1;
uint32_t reserved_25a : 32;
#endif
};
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000
#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26
#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26
#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000
#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53
#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53
#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000
#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0
#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11
#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000
#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21
#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24
#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000
#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25
#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25
#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000
#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25
#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27
#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000
#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB 5
#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB 5
#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK 0x0000000000000020
#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB 6
#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB 6
#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK 0x0000000000000040
#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB 7
#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB 7
#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK 0x0000000000000080
#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB 8
#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB 11
#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000000000f00
#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB 12
#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB 12
#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK 0x0000000000001000
#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB 13
#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB 14
#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK 0x0000000000006000
#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB 15
#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB 18
#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK 0x0000000000078000
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB 19
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB 19
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK 0x0000000000080000
#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB 20
#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB 24
#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK 0x0000000001f00000
#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 25
#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 25
#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x0000000002000000
#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB 26
#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB 31
#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK 0x00000000fc000000
#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB 32
#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB 47
#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK 0x0000ffff00000000
#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000058
#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 48
#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 63
#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0xffff000000000000
#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_OFFSET 0x0000000000000060
#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_LSB 1
#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MSB 1
#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MASK 0x0000000000000002
#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_OFFSET 0x0000000000000060
#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_LSB 2
#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MSB 2
#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MASK 0x0000000000000004
#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET 0x0000000000000060
#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB 3
#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB 31
#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK 0x00000000fffffff8
#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET 0x0000000000000060
#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB 32
#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB 63
#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK 0xffffffff00000000
#endif

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hw/wcn8750/v1/pcu_ppdu_setup_init.h Normal file
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hw/wcn8750/v1/pdg_response.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PDG_RESPONSE_H_
#define _PDG_RESPONSE_H_
#include "pdg_response_rate_setting.h"
#define NUM_OF_DWORDS_PDG_RESPONSE 14
#define NUM_OF_QWORDS_PDG_RESPONSE 7
struct pdg_response {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct pdg_response_rate_setting hw_response_rate_info;
uint32_t hw_response_tx_duration : 16,
rx_duration_field : 16;
uint32_t punctured_response_transmission : 1,
cca_subband_channel_bonding_mask : 16,
scrambler_seed_override : 2,
response_density_valid : 1,
response_density : 5,
more_data : 1,
duration_indication : 1,
blackout_details_en : 1,
cfp_protected_resp : 1,
bandwidth : 3;
uint32_t ack_id : 16,
block_ack_bitmap : 16;
uint32_t response_frame_type : 4,
ack_id_ext : 10,
ftm_en : 1,
group_id : 6,
sta_partial_aid : 11;
uint32_t ndp_ba_start_seq_ctrl : 12,
active_channel : 3,
txop_duration_all_ones : 1,
frame_length : 16;
uint32_t dso_primary20_index_select : 4,
dso_freq_subband_channel_bonding_mask : 16,
pad_duration : 5,
q2q_mba : 1,
reserved_12a : 6;
uint32_t tlv64_padding : 32;
#else
struct pdg_response_rate_setting hw_response_rate_info;
uint32_t rx_duration_field : 16,
hw_response_tx_duration : 16;
uint32_t bandwidth : 3,
cfp_protected_resp : 1,
blackout_details_en : 1,
duration_indication : 1,
more_data : 1,
response_density : 5,
response_density_valid : 1,
scrambler_seed_override : 2,
cca_subband_channel_bonding_mask : 16,
punctured_response_transmission : 1;
uint32_t block_ack_bitmap : 16,
ack_id : 16;
uint32_t sta_partial_aid : 11,
group_id : 6,
ftm_en : 1,
ack_id_ext : 10,
response_frame_type : 4;
uint32_t frame_length : 16,
txop_duration_all_ones : 1,
active_channel : 3,
ndp_ba_start_seq_ctrl : 12;
uint32_t reserved_12a : 6,
q2q_mba : 1,
pad_duration : 5,
dso_freq_subband_channel_bonding_mask : 16,
dso_primary20_index_select : 4;
uint32_t tlv64_padding : 32;
#endif
};
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB 0
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB 3
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK 0x000000000000000f
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 32
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 36
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000001f00000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 37
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000e000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 46
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00007c0000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB 47
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB 47
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK 0x0000800000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000
#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018
#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48
#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63
#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000
#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020
#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20
#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24
#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000
#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020
#define PDG_RESPONSE_MORE_DATA_LSB 25
#define PDG_RESPONSE_MORE_DATA_MSB 25
#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000
#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020
#define PDG_RESPONSE_DURATION_INDICATION_LSB 26
#define PDG_RESPONSE_DURATION_INDICATION_MSB 26
#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000
#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000020
#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB 27
#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB 27
#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK 0x0000000008000000
#define PDG_RESPONSE_CFP_PROTECTED_RESP_OFFSET 0x0000000000000020
#define PDG_RESPONSE_CFP_PROTECTED_RESP_LSB 28
#define PDG_RESPONSE_CFP_PROTECTED_RESP_MSB 28
#define PDG_RESPONSE_CFP_PROTECTED_RESP_MASK 0x0000000010000000
#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020
#define PDG_RESPONSE_BANDWIDTH_LSB 29
#define PDG_RESPONSE_BANDWIDTH_MSB 31
#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000
#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020
#define PDG_RESPONSE_ACK_ID_LSB 32
#define PDG_RESPONSE_ACK_ID_MSB 47
#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f
#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028
#define PDG_RESPONSE_ACK_ID_EXT_LSB 4
#define PDG_RESPONSE_ACK_ID_EXT_MSB 13
#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0
#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028
#define PDG_RESPONSE_FTM_EN_LSB 14
#define PDG_RESPONSE_FTM_EN_MSB 14
#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000
#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028
#define PDG_RESPONSE_GROUP_ID_LSB 15
#define PDG_RESPONSE_GROUP_ID_MSB 20
#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000
#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028
#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21
#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31
#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000
#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028
#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44
#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46
#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000
#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028
#define PDG_RESPONSE_FRAME_LENGTH_LSB 48
#define PDG_RESPONSE_FRAME_LENGTH_MSB 63
#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000
#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000030
#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB 0
#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB 3
#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK 0x000000000000000f
#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000030
#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 4
#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 19
#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x00000000000ffff0
#define PDG_RESPONSE_PAD_DURATION_OFFSET 0x0000000000000030
#define PDG_RESPONSE_PAD_DURATION_LSB 20
#define PDG_RESPONSE_PAD_DURATION_MSB 24
#define PDG_RESPONSE_PAD_DURATION_MASK 0x0000000001f00000
#define PDG_RESPONSE_Q2Q_MBA_OFFSET 0x0000000000000030
#define PDG_RESPONSE_Q2Q_MBA_LSB 25
#define PDG_RESPONSE_Q2Q_MBA_MSB 25
#define PDG_RESPONSE_Q2Q_MBA_MASK 0x0000000002000000
#define PDG_RESPONSE_RESERVED_12A_OFFSET 0x0000000000000030
#define PDG_RESPONSE_RESERVED_12A_LSB 26
#define PDG_RESPONSE_RESERVED_12A_MSB 31
#define PDG_RESPONSE_RESERVED_12A_MASK 0x00000000fc000000
#define PDG_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000030
#define PDG_RESPONSE_TLV64_PADDING_LSB 32
#define PDG_RESPONSE_TLV64_PADDING_MSB 63
#define PDG_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

409
hw/wcn8750/v1/pdg_response_rate_setting.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PDG_RESPONSE_RATE_SETTING_H_
#define _PDG_RESPONSE_RATE_SETTING_H_
#include "mlo_sta_id_details.h"
#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
struct pdg_response_rate_setting {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t reserved_0a : 1,
tx_antenna_sector_ctrl : 24,
pkt_type : 4,
smoothing : 1,
ldpc : 1,
stbc : 1;
uint32_t alt_tx_pwr : 8,
alt_min_tx_pwr : 8,
alt_nss : 3,
alt_tx_chain_mask : 8,
alt_bw : 3,
stf_ltf_3db_boost : 1,
force_extra_symbol : 1;
uint32_t reserved_2a : 4,
nss : 3,
dpd_enable : 1,
tx_pwr : 8,
min_tx_pwr : 8,
tx_chain_mask : 8;
uint32_t alt_rate_mcs : 5,
reserved_3a : 3,
sgi : 2,
rate_mcs : 5,
ldpc_2x_codeword : 1,
tx_pwr_1 : 8,
alt_tx_pwr_1 : 8;
uint32_t aggregation : 1,
dot11ax_bss_color_id : 6,
dot11ax_spatial_reuse : 4,
dot11ax_cp_ltf_size : 2,
dot11ax_dcm : 1,
dot11ax_doppler_indication : 1,
dot11ax_su_extended : 1,
dot11ax_min_packet_extension : 2,
dot11ax_pe_nss : 3,
dot11ax_pe_content : 1,
dot11ax_pe_ltf_size : 2,
dot11ax_chain_csd_en : 1,
dot11ax_pe_chain_csd_en : 1,
dot11ax_dl_ul_flag : 1,
reserved_4a : 5;
uint32_t dot11ax_ext_ru_start_index : 4,
dot11ax_ext_ru_size : 4,
eht_duplicate_mode : 2,
he_sigb_dcm : 1,
he_sigb_0_mcs : 3,
num_he_sigb_sym : 5,
required_response_time_source : 1,
reserved_5a : 6,
u_sig_puncture_pattern_encoding : 6;
struct mlo_sta_id_details mlo_sta_id_details_rx;
uint16_t required_response_time : 12,
dot11be_params_placeholder : 4;
#else
uint32_t stbc : 1,
ldpc : 1,
smoothing : 1,
pkt_type : 4,
tx_antenna_sector_ctrl : 24,
reserved_0a : 1;
uint32_t force_extra_symbol : 1,
stf_ltf_3db_boost : 1,
alt_bw : 3,
alt_tx_chain_mask : 8,
alt_nss : 3,
alt_min_tx_pwr : 8,
alt_tx_pwr : 8;
uint32_t tx_chain_mask : 8,
min_tx_pwr : 8,
tx_pwr : 8,
dpd_enable : 1,
nss : 3,
reserved_2a : 4;
uint32_t alt_tx_pwr_1 : 8,
tx_pwr_1 : 8,
ldpc_2x_codeword : 1,
rate_mcs : 5,
sgi : 2,
reserved_3a : 3,
alt_rate_mcs : 5;
uint32_t reserved_4a : 5,
dot11ax_dl_ul_flag : 1,
dot11ax_pe_chain_csd_en : 1,
dot11ax_chain_csd_en : 1,
dot11ax_pe_ltf_size : 2,
dot11ax_pe_content : 1,
dot11ax_pe_nss : 3,
dot11ax_min_packet_extension : 2,
dot11ax_su_extended : 1,
dot11ax_doppler_indication : 1,
dot11ax_dcm : 1,
dot11ax_cp_ltf_size : 2,
dot11ax_spatial_reuse : 4,
dot11ax_bss_color_id : 6,
aggregation : 1;
uint32_t u_sig_puncture_pattern_encoding : 6,
reserved_5a : 6,
required_response_time_source : 1,
num_he_sigb_sym : 5,
he_sigb_0_mcs : 3,
he_sigb_dcm : 1,
eht_duplicate_mode : 2,
dot11ax_ext_ru_size : 4,
dot11ax_ext_ru_start_index : 4;
uint32_t dot11be_params_placeholder : 4,
required_response_time : 12;
struct mlo_sta_id_details mlo_sta_id_details_rx;
#endif
};
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000
#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000
#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30
#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30
#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000
#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000
#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31
#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31
#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000
#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET 0x00000008
#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB 0
#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB 3
#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK 0x0000000f
#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008
#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4
#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6
#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x0000000c
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 4
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000001f
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 5
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000e0
#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c
#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8
#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9
#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 14
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00007c00
#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET 0x0000000c
#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB 15
#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB 15
#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK 0x00008000
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
#endif

89
hw/wcn8750/v1/pdg_tx_req.h Normal file
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@ -0,0 +1,89 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PDG_TX_REQ_H_
#define _PDG_TX_REQ_H_
#define NUM_OF_DWORDS_PDG_TX_REQ 2
#define NUM_OF_QWORDS_PDG_TX_REQ 1
struct pdg_tx_req {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t tx_reason : 2,
use_puncture_pattern : 2,
req_bw : 3,
puncture_pattern_number : 6,
reserved_0b : 1,
req_paprd : 1,
duration_field_boundary_valid : 1,
duration_field_boundary : 16;
uint32_t puncture_subband_mask : 16,
reserved_0c : 16;
#else
uint32_t duration_field_boundary : 16,
duration_field_boundary_valid : 1,
req_paprd : 1,
reserved_0b : 1,
puncture_pattern_number : 6,
req_bw : 3,
use_puncture_pattern : 2,
tx_reason : 2;
uint32_t reserved_0c : 16,
puncture_subband_mask : 16;
#endif
};
#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000
#define PDG_TX_REQ_TX_REASON_LSB 0
#define PDG_TX_REQ_TX_REASON_MSB 1
#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c
#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000
#define PDG_TX_REQ_REQ_BW_LSB 4
#define PDG_TX_REQ_REQ_BW_MSB 6
#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80
#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000
#define PDG_TX_REQ_RESERVED_0B_LSB 13
#define PDG_TX_REQ_RESERVED_0B_MSB 13
#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000
#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000
#define PDG_TX_REQ_REQ_PAPRD_LSB 14
#define PDG_TX_REQ_REQ_PAPRD_MSB 14
#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000
#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000
#define PDG_TX_REQ_RESERVED_0C_LSB 48
#define PDG_TX_REQ_RESERVED_0C_MSB 63
#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
#define _PHYRX_ABORT_REQUEST_INFO_H_
#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
struct phyrx_abort_request_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t phyrx_abort_reason : 8,
phy_enters_nap_state : 1,
phy_enters_defer_state : 1,
gain_change_by_main : 1,
gain_change_by_bt : 1,
main_tx_indication : 1,
bt_tx_indication : 1,
concurrent_mode : 1,
reserved_0 : 1,
receive_duration : 16;
#else
uint32_t receive_duration : 16,
reserved_0 : 1,
concurrent_mode : 1,
bt_tx_indication : 1,
main_tx_indication : 1,
gain_change_by_bt : 1,
gain_change_by_main : 1,
phy_enters_defer_state : 1,
phy_enters_nap_state : 1,
phyrx_abort_reason : 8;
#endif
};
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800
#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12
#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12
#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000
#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13
#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13
#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000
#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14
#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14
#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_COMMON_USER_INFO_H_
#define _PHYRX_COMMON_USER_INFO_H_
#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2
struct phyrx_common_user_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t receive_duration : 16,
reserved_0a : 16;
uint32_t u_sig_puncture_pattern_encoding : 6,
eht___reserved_g_0005_ndp : 1,
reserved_1a : 8,
obss_nav_update_enable : 1,
obss_nav_value : 16;
uint32_t eht_or_uhr_ppdu_type : 2,
bss_color_id : 6,
dl_ul_flag : 1,
txop_duration : 7,
cp_setting : 2,
ltf_size : 2,
spatial_reuse : 4,
rx_ndp : 1,
dot11bn_su_elr : 1,
reserved_2a : 6;
uint32_t eht_duplicate : 2,
eht_or_uhr_sig_cmn_field_type : 2,
doppler_indication : 1,
sta_id : 11,
puncture_bitmap : 16;
#else
uint32_t reserved_0a : 16,
receive_duration : 16;
uint32_t obss_nav_value : 16,
obss_nav_update_enable : 1,
reserved_1a : 8,
eht___reserved_g_0005_ndp : 1,
u_sig_puncture_pattern_encoding : 6;
uint32_t reserved_2a : 6,
dot11bn_su_elr : 1,
rx_ndp : 1,
spatial_reuse : 4,
ltf_size : 2,
cp_setting : 2,
txop_duration : 7,
dl_ul_flag : 1,
bss_color_id : 6,
eht_or_uhr_ppdu_type : 2;
uint32_t puncture_bitmap : 16,
sta_id : 11,
doppler_indication : 1,
eht_or_uhr_sig_cmn_field_type : 2,
eht_duplicate : 2;
#endif
};
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 39
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 46
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007f8000000000
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 47
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 47
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x0000800000000000
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 48
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 63
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff000000000000
#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB 0
#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB 1
#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK 0x0000000000000003
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00
#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000
#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24
#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24
#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000
#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB 25
#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB 25
#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK 0x0000000002000000
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000
#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB 34
#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB 35
#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000
#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37
#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47
#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
#define _PHYRX_HE_SIG_A_MU_DL_H_
#include "he_sig_a_mu_dl_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1
struct phyrx_he_sig_a_mu_dl {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
#else
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
#endif
};
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
#define _PHYRX_HE_SIG_A_MU_UL_H_
#include "he_sig_a_mu_ul_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1
struct phyrx_he_sig_a_mu_ul {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
#else
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
#endif
};
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_HE_SIG_A_SU_H_
#define _PHYRX_HE_SIG_A_SU_H_
#include "he_sig_a_su_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1
struct phyrx_he_sig_a_su {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
#else
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
#endif
};
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

44
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_HE_SIG_B1_MU_H_
#define _PHYRX_HE_SIG_B1_MU_H_
#include "he_sig_b1_mu_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1
struct phyrx_he_sig_b1_mu {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
uint32_t tlv64_padding : 32;
#else
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
uint32_t tlv64_padding : 32;
#endif
};
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_HE_SIG_B2_MU_H_
#define _PHYRX_HE_SIG_B2_MU_H_
#include "he_sig_b2_mu_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1
struct phyrx_he_sig_b2_mu {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
#else
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
#endif
};
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
#define _PHYRX_HE_SIG_B2_OFDMA_H_
#include "he_sig_b2_ofdma_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1
struct phyrx_he_sig_b2_ofdma {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
#else
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
#endif
};
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_HT_SIG_H_
#define _PHYRX_HT_SIG_H_
#include "ht_sig_info.h"
#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
#define NUM_OF_QWORDS_PHYRX_HT_SIG 1
struct phyrx_ht_sig {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct ht_sig_info phyrx_ht_sig_info_details;
#else
struct ht_sig_info phyrx_ht_sig_info_details;
#endif
};
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

74
hw/wcn8750/v1/phyrx_l_sig_a.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_L_SIG_A_H_
#define _PHYRX_L_SIG_A_H_
#include "l_sig_a_info.h"
#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2
#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1
struct phyrx_l_sig_a {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct l_sig_a_info phyrx_l_sig_a_info_details;
uint32_t tlv64_padding : 32;
#else
struct l_sig_a_info phyrx_l_sig_a_info_details;
uint32_t tlv64_padding : 32;
#endif
};
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32
#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63
#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000
#endif

49
hw/wcn8750/v1/phyrx_l_sig_b.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_L_SIG_B_H_
#define _PHYRX_L_SIG_B_H_
#include "l_sig_b_info.h"
#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2
#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1
struct phyrx_l_sig_b {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct l_sig_b_info phyrx_l_sig_b_info_details;
uint32_t tlv64_padding : 32;
#else
struct l_sig_b_info phyrx_l_sig_b_info_details;
uint32_t tlv64_padding : 32;
#endif
};
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32
#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63
#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000
#endif

332
hw/wcn8750/v1/phyrx_location.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_LOCATION_H_
#define _PHYRX_LOCATION_H_
#include "rx_location_info.h"
#define NUM_OF_DWORDS_PHYRX_LOCATION 28
#define NUM_OF_QWORDS_PHYRX_LOCATION 14
struct phyrx_location {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct rx_location_info rx_location_info_details;
#else
struct rx_location_info rx_location_info_details;
#endif
};
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000
#endif

47
hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4
#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2
struct phyrx_other_receive_info_ru_details {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t ru_details_channel_0 : 32;
uint32_t ru_details_channel_1 : 32;
uint32_t spare : 32;
uint32_t tlv64_padding : 32;
#else
uint32_t ru_details_channel_0 : 32;
uint32_t ru_details_channel_1 : 32;
uint32_t spare : 32;
uint32_t tlv64_padding : 32;
#endif
};
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000
#endif

427
hw/wcn8750/v1/phyrx_pkt_end.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_PKT_END_H_
#define _PHYRX_PKT_END_H_
#include "phyrx_pkt_end_info.h"
#define NUM_OF_DWORDS_PHYRX_PKT_END 24
#define NUM_OF_QWORDS_PHYRX_PKT_END 12
struct phyrx_pkt_end {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct phyrx_pkt_end_info rx_pkt_end_details;
#else
struct phyrx_pkt_end_info rx_pkt_end_details;
#endif
};
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 54
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc0000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000
#endif

450
hw/wcn8750/v1/phyrx_pkt_end_info.h Normal file
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@ -0,0 +1,450 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_PKT_END_INFO_H_
#define _PHYRX_PKT_END_INFO_H_
#include "receive_rssi_info.h"
#include "rx_timing_info.h"
#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24
struct phyrx_pkt_end_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t __reserved_g_0001 : 1,
location_info_valid : 1,
timing_info_valid : 1,
rssi_info_valid : 1,
reserved_0a : 1,
frameless_frame_received : 1,
reserved_0b : 2,
rssi_comb : 8,
reserved_0c : 16;
struct rx_timing_info rx_timing_info_details;
struct receive_rssi_info post_rssi_info_details;
uint32_t phy_sw_status_31_0 : 32;
uint32_t phy_sw_status_63_32 : 32;
#else
uint32_t reserved_0c : 16,
rssi_comb : 8,
reserved_0b : 2,
frameless_frame_received : 1,
reserved_0a : 1,
rssi_info_valid : 1,
timing_info_valid : 1,
location_info_valid : 1,
__reserved_g_0001 : 1;
struct rx_timing_info rx_timing_info_details;
struct receive_rssi_info post_rssi_info_details;
uint32_t phy_sw_status_31_0 : 32;
uint32_t phy_sw_status_63_32 : 32;
#endif
};
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008
#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4
#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4
#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6
#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7
#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0
#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8
#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15
#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16
#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31
#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x00000014
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 12
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 21
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff000
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 22
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc00000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff
#endif

806
hw/wcn8750/v1/phyrx_rssi_legacy.h Normal file
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@ -0,0 +1,806 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_RSSI_LEGACY_H_
#define _PHYRX_RSSI_LEGACY_H_
#include "receive_rssi_info.h"
#include "receive_pkt_start_info.h"
#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42
#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21
struct phyrx_rssi_legacy {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct receive_pkt_start_info rx_pkt_start_details;
uint32_t sw_phy_meta_data : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
struct receive_rssi_info pre_rssi_info_details;
struct receive_rssi_info preamble_rssi_info_details;
uint32_t pre_rssi_comb : 8,
rssi_comb : 8,
normalized_pre_rssi_comb : 8,
normalized_rssi_comb : 8;
uint32_t rssi_comb_ppdu : 8,
rssi_db_to_dbm_offset : 8,
rssi_for_spatial_reuse : 8,
rssi_for_trigger_resp : 8;
#else
struct receive_pkt_start_info rx_pkt_start_details;
uint32_t sw_phy_meta_data : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
struct receive_rssi_info pre_rssi_info_details;
struct receive_rssi_info preamble_rssi_info_details;
uint32_t normalized_rssi_comb : 8,
normalized_pre_rssi_comb : 8,
rssi_comb : 8,
pre_rssi_comb : 8;
uint32_t rssi_for_trigger_resp : 8,
rssi_for_spatial_reuse : 8,
rssi_db_to_dbm_offset : 8,
rssi_comb_ppdu : 8;
#endif
};
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x000000000000000f
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 32
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 63
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff00000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000008
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 32
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 39
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000000000008
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 40
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 40
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x0000010000000000
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 41
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 63
#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe0000000000
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000010
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0x00000000ffffffff
#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010
#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 32
#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 63
#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff00000000
#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018
#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0
#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31
#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff
#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018
#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32
#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63
#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000
#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0
#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7
#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff
#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0
#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8
#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15
#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00
#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0
#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16
#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23
#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000
#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0
#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24
#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31
#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000
#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0
#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32
#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39
#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000
#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0
#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40
#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47
#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000
#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0
#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48
#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55
#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000
#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0
#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56
#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63
#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_USER_INFO_H_
#define _PHYRX_USER_INFO_H_
#include "receive_user_info.h"
#define NUM_OF_DWORDS_PHYRX_USER_INFO 8
#define NUM_OF_QWORDS_PHYRX_USER_INFO 4
struct phyrx_user_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct receive_user_info receive_user_info_details;
#else
struct receive_user_info receive_user_info_details;
#endif
};
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYRX_VHT_SIG_A_H_
#define _PHYRX_VHT_SIG_A_H_
#include "vht_sig_a_info.h"
#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1
struct phyrx_vht_sig_a {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct vht_sig_a_info phyrx_vht_sig_a_info_details;
#else
struct vht_sig_a_info phyrx_vht_sig_a_info_details;
#endif
};
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

38
hw/wcn8750/v1/phytx_abort_request_info.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
#define _PHYTX_ABORT_REQUEST_INFO_H_
#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
struct phytx_abort_request_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint16_t phytx_abort_reason : 8,
user_number : 6,
reserved : 2;
#else
uint16_t reserved : 2,
user_number : 6,
phytx_abort_reason : 8;
#endif
};
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYTX_PKT_END_H_
#define _PHYTX_PKT_END_H_
#define NUM_OF_WORDS_PHYTX_PKT_END 28
#define NUM_OF_DWORDS_PHYTX_PKT_END 14
struct phytx_pkt_end {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint16_t start_of_frame_timestamp_15_0 : 16;
uint16_t start_of_frame_timestamp_31_16 : 16;
uint16_t end_of_frame_timestamp_15_0 : 16;
uint16_t end_of_frame_timestamp_31_16 : 16;
uint16_t tx_group_delay : 12,
timing_status : 2,
phyrx_entered_nap_state : 1,
dpdtrain_done : 1;
uint16_t transmit_delay : 16;
uint16_t tpc_dbg_info_cmn_15_0 : 16;
uint16_t tpc_dbg_info_cmn_31_16 : 16;
uint16_t tpc_dbg_info_cmn_47_32 : 16;
uint16_t tpc_dbg_info_chn1_15_0 : 16;
uint16_t tpc_dbg_info_chn1_31_16 : 16;
uint16_t tpc_dbg_info_chn1_47_32 : 16;
uint16_t tpc_dbg_info_chn1_63_48 : 16;
uint16_t tpc_dbg_info_chn1_79_64 : 16;
uint16_t tpc_dbg_info_chn2_15_0 : 16;
uint16_t tpc_dbg_info_chn2_31_16 : 16;
uint16_t tpc_dbg_info_chn2_47_32 : 16;
uint16_t tpc_dbg_info_chn2_63_48 : 16;
uint16_t tpc_dbg_info_chn2_79_64 : 16;
uint16_t phytx_tx_end_sw_info_15_0 : 16;
uint16_t phytx_tx_end_sw_info_31_16 : 16;
uint16_t phytx_tx_end_sw_info_47_32 : 16;
uint16_t phytx_tx_end_sw_info_63_48 : 16;
uint16_t beamform_masked_user_bitmap_15_0 : 16;
uint16_t beamform_masked_user_bitmap_31_16 : 16;
uint16_t beamform_masked_user_bitmap_36_32 : 5,
reserved_23 : 11;
uint16_t reserved_26 : 16;
uint16_t reserved_27 : 16;
#else
uint16_t start_of_frame_timestamp_15_0 : 16;
uint16_t start_of_frame_timestamp_31_16 : 16;
uint16_t end_of_frame_timestamp_15_0 : 16;
uint16_t end_of_frame_timestamp_31_16 : 16;
uint16_t dpdtrain_done : 1,
phyrx_entered_nap_state : 1,
timing_status : 2,
tx_group_delay : 12;
uint16_t transmit_delay : 16;
uint16_t tpc_dbg_info_cmn_15_0 : 16;
uint16_t tpc_dbg_info_cmn_31_16 : 16;
uint16_t tpc_dbg_info_cmn_47_32 : 16;
uint16_t tpc_dbg_info_chn1_15_0 : 16;
uint16_t tpc_dbg_info_chn1_31_16 : 16;
uint16_t tpc_dbg_info_chn1_47_32 : 16;
uint16_t tpc_dbg_info_chn1_63_48 : 16;
uint16_t tpc_dbg_info_chn1_79_64 : 16;
uint16_t tpc_dbg_info_chn2_15_0 : 16;
uint16_t tpc_dbg_info_chn2_31_16 : 16;
uint16_t tpc_dbg_info_chn2_47_32 : 16;
uint16_t tpc_dbg_info_chn2_63_48 : 16;
uint16_t tpc_dbg_info_chn2_79_64 : 16;
uint16_t phytx_tx_end_sw_info_15_0 : 16;
uint16_t phytx_tx_end_sw_info_31_16 : 16;
uint16_t phytx_tx_end_sw_info_47_32 : 16;
uint16_t phytx_tx_end_sw_info_63_48 : 16;
uint16_t beamform_masked_user_bitmap_15_0 : 16;
uint16_t beamform_masked_user_bitmap_31_16 : 16;
uint16_t reserved_23 : 11,
beamform_masked_user_bitmap_36_32 : 5;
uint16_t reserved_26 : 16;
uint16_t reserved_27 : 16;
#endif
};
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff
#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008
#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0
#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11
#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff
#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008
#define PHYTX_PKT_END_TIMING_STATUS_LSB 12
#define PHYTX_PKT_END_TIMING_STATUS_MSB 13
#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000
#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008
#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14
#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14
#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000
#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008
#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15
#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15
#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000
#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a
#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0
#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15
#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f
#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032
#define PHYTX_PKT_END_RESERVED_23_LSB 5
#define PHYTX_PKT_END_RESERVED_23_MSB 15
#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0
#define PHYTX_PKT_END_RESERVED_26_OFFSET 0x00000034
#define PHYTX_PKT_END_RESERVED_26_LSB 0
#define PHYTX_PKT_END_RESERVED_26_MSB 15
#define PHYTX_PKT_END_RESERVED_26_MASK 0x0000ffff
#define PHYTX_PKT_END_RESERVED_27_OFFSET 0x00000036
#define PHYTX_PKT_END_RESERVED_27_LSB 0
#define PHYTX_PKT_END_RESERVED_27_MSB 15
#define PHYTX_PKT_END_RESERVED_27_MASK 0x0000ffff
#endif

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hw/wcn8750/v1/phytx_ppdu_header_info_request.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2
#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1
struct phytx_ppdu_header_info_request {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint16_t request_type : 5,
reserved : 11;
uint16_t tlv32_padding : 16;
#else
uint16_t reserved : 11,
request_type : 5;
uint16_t tlv32_padding : 16;
#endif
};
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RECEIVE_PKT_START_INFO_H_
#define _RECEIVE_PKT_START_INFO_H_
#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4
struct receive_pkt_start_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t reception_type : 4,
rx_chain_mask_type : 1,
receive_bandwidth : 3,
rx_chain_mask : 8,
phy_ppdu_id : 16;
uint32_t ppdu_start_timestamp_31_0 : 32;
uint32_t ppdu_start_timestamp_63_32 : 32;
uint32_t preamble_time_to_rxframe : 8,
standalone_sniffer_mode : 1,
reserved_3a : 23;
#else
uint32_t phy_ppdu_id : 16,
rx_chain_mask : 8,
receive_bandwidth : 3,
rx_chain_mask_type : 1,
reception_type : 4;
uint32_t ppdu_start_timestamp_31_0 : 32;
uint32_t ppdu_start_timestamp_63_32 : 32;
uint32_t reserved_3a : 23,
standalone_sniffer_mode : 1,
preamble_time_to_rxframe : 8;
#endif
};
#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000
#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0
#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3
#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010
#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000
#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5
#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7
#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00
#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000
#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16
#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31
#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c
#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0
#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7
#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff
#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c
#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8
#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8
#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100
#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c
#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9
#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31
#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00
#endif

465
hw/wcn8750/v1/receive_rssi_info.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RECEIVE_RSSI_INFO_H_
#define _RECEIVE_RSSI_INFO_H_
#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
struct receive_rssi_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t rssi_pri20_chain0 : 8,
rssi_ext20_chain0 : 8,
rssi_ext40_low20_chain0 : 8,
rssi_ext40_high20_chain0 : 8;
uint32_t rssi_ext80_low20_chain0 : 8,
rssi_ext80_low_high20_chain0 : 8,
rssi_ext80_high_low20_chain0 : 8,
rssi_ext80_high20_chain0 : 8;
uint32_t rssi_ext160_0_chain0 : 8,
rssi_ext160_1_chain0 : 8,
rssi_ext160_2_chain0 : 8,
rssi_ext160_3_chain0 : 8;
uint32_t rssi_ext160_4_chain0 : 8,
rssi_ext160_5_chain0 : 8,
rssi_ext160_6_chain0 : 8,
rssi_ext160_7_chain0 : 8;
uint32_t rssi_pri20_chain1 : 8,
rssi_ext20_chain1 : 8,
rssi_ext40_low20_chain1 : 8,
rssi_ext40_high20_chain1 : 8;
uint32_t rssi_ext80_low20_chain1 : 8,
rssi_ext80_low_high20_chain1 : 8,
rssi_ext80_high_low20_chain1 : 8,
rssi_ext80_high20_chain1 : 8;
uint32_t rssi_ext160_0_chain1 : 8,
rssi_ext160_1_chain1 : 8,
rssi_ext160_2_chain1 : 8,
rssi_ext160_3_chain1 : 8;
uint32_t rssi_ext160_4_chain1 : 8,
rssi_ext160_5_chain1 : 8,
rssi_ext160_6_chain1 : 8,
rssi_ext160_7_chain1 : 8;
uint32_t rssi_pri20_chain2 : 8,
rssi_ext20_chain2 : 8,
rssi_ext40_low20_chain2 : 8,
rssi_ext40_high20_chain2 : 8;
uint32_t rssi_ext80_low20_chain2 : 8,
rssi_ext80_low_high20_chain2 : 8,
rssi_ext80_high_low20_chain2 : 8,
rssi_ext80_high20_chain2 : 8;
uint32_t rssi_ext160_0_chain2 : 8,
rssi_ext160_1_chain2 : 8,
rssi_ext160_2_chain2 : 8,
rssi_ext160_3_chain2 : 8;
uint32_t rssi_ext160_4_chain2 : 8,
rssi_ext160_5_chain2 : 8,
rssi_ext160_6_chain2 : 8,
rssi_ext160_7_chain2 : 8;
uint32_t rssi_pri20_chain3 : 8,
rssi_ext20_chain3 : 8,
rssi_ext40_low20_chain3 : 8,
rssi_ext40_high20_chain3 : 8;
uint32_t rssi_ext80_low20_chain3 : 8,
rssi_ext80_low_high20_chain3 : 8,
rssi_ext80_high_low20_chain3 : 8,
rssi_ext80_high20_chain3 : 8;
uint32_t rssi_ext160_0_chain3 : 8,
rssi_ext160_1_chain3 : 8,
rssi_ext160_2_chain3 : 8,
rssi_ext160_3_chain3 : 8;
uint32_t rssi_ext160_4_chain3 : 8,
rssi_ext160_5_chain3 : 8,
rssi_ext160_6_chain3 : 8,
rssi_ext160_7_chain3 : 8;
#else
uint32_t rssi_ext40_high20_chain0 : 8,
rssi_ext40_low20_chain0 : 8,
rssi_ext20_chain0 : 8,
rssi_pri20_chain0 : 8;
uint32_t rssi_ext80_high20_chain0 : 8,
rssi_ext80_high_low20_chain0 : 8,
rssi_ext80_low_high20_chain0 : 8,
rssi_ext80_low20_chain0 : 8;
uint32_t rssi_ext160_3_chain0 : 8,
rssi_ext160_2_chain0 : 8,
rssi_ext160_1_chain0 : 8,
rssi_ext160_0_chain0 : 8;
uint32_t rssi_ext160_7_chain0 : 8,
rssi_ext160_6_chain0 : 8,
rssi_ext160_5_chain0 : 8,
rssi_ext160_4_chain0 : 8;
uint32_t rssi_ext40_high20_chain1 : 8,
rssi_ext40_low20_chain1 : 8,
rssi_ext20_chain1 : 8,
rssi_pri20_chain1 : 8;
uint32_t rssi_ext80_high20_chain1 : 8,
rssi_ext80_high_low20_chain1 : 8,
rssi_ext80_low_high20_chain1 : 8,
rssi_ext80_low20_chain1 : 8;
uint32_t rssi_ext160_3_chain1 : 8,
rssi_ext160_2_chain1 : 8,
rssi_ext160_1_chain1 : 8,
rssi_ext160_0_chain1 : 8;
uint32_t rssi_ext160_7_chain1 : 8,
rssi_ext160_6_chain1 : 8,
rssi_ext160_5_chain1 : 8,
rssi_ext160_4_chain1 : 8;
uint32_t rssi_ext40_high20_chain2 : 8,
rssi_ext40_low20_chain2 : 8,
rssi_ext20_chain2 : 8,
rssi_pri20_chain2 : 8;
uint32_t rssi_ext80_high20_chain2 : 8,
rssi_ext80_high_low20_chain2 : 8,
rssi_ext80_low_high20_chain2 : 8,
rssi_ext80_low20_chain2 : 8;
uint32_t rssi_ext160_3_chain2 : 8,
rssi_ext160_2_chain2 : 8,
rssi_ext160_1_chain2 : 8,
rssi_ext160_0_chain2 : 8;
uint32_t rssi_ext160_7_chain2 : 8,
rssi_ext160_6_chain2 : 8,
rssi_ext160_5_chain2 : 8,
rssi_ext160_4_chain2 : 8;
uint32_t rssi_ext40_high20_chain3 : 8,
rssi_ext40_low20_chain3 : 8,
rssi_ext20_chain3 : 8,
rssi_pri20_chain3 : 8;
uint32_t rssi_ext80_high20_chain3 : 8,
rssi_ext80_high_low20_chain3 : 8,
rssi_ext80_low_high20_chain3 : 8,
rssi_ext80_low20_chain3 : 8;
uint32_t rssi_ext160_3_chain3 : 8,
rssi_ext160_2_chain3 : 8,
rssi_ext160_1_chain3 : 8,
rssi_ext160_0_chain3 : 8;
uint32_t rssi_ext160_7_chain3 : 8,
rssi_ext160_6_chain3 : 8,
rssi_ext160_5_chain3 : 8,
rssi_ext160_4_chain3 : 8;
#endif
};
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RECEIVE_USER_INFO_H_
#define _RECEIVE_USER_INFO_H_
#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
struct receive_user_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t phy_ppdu_id : 16,
user_rssi : 8,
pkt_type : 4,
stbc : 1,
reception_type : 3;
uint32_t rate_mcs : 5,
sgi : 2,
__reserved_g_0004 : 1,
mimo_ss_bitmap : 8,
receive_bandwidth : 3,
reserved_1b : 5,
dl_ofdma_user_index : 8;
uint32_t dl_ofdma_content_channel : 1,
reserved_2a : 1,
qam_diff1 : 2,
qam_diff2 : 2,
qam_diff3 : 2,
nss : 3,
stream_offset : 3,
sta_dcm : 1,
ldpc : 1,
ru_type_80_0 : 4,
ru_type_80_1 : 4,
ru_type_80_2 : 4,
ru_type_80_3 : 4;
uint32_t ru_start_index_80_0 : 6,
reserved_3a : 2,
ru_start_index_80_1 : 6,
reserved_3b : 2,
ru_start_index_80_2 : 6,
reserved_3c : 2,
ru_start_index_80_3 : 6,
reserved_3d : 2;
uint32_t user_fd_rssi_seg0 : 32;
uint32_t user_fd_rssi_seg1 : 32;
uint32_t user_fd_rssi_seg2 : 32;
uint32_t user_fd_rssi_seg3 : 32;
#else
uint32_t reception_type : 3,
stbc : 1,
pkt_type : 4,
user_rssi : 8,
phy_ppdu_id : 16;
uint32_t dl_ofdma_user_index : 8,
reserved_1b : 5,
receive_bandwidth : 3,
mimo_ss_bitmap : 8,
__reserved_g_0004 : 1,
sgi : 2,
rate_mcs : 5;
uint32_t ru_type_80_3 : 4,
ru_type_80_2 : 4,
ru_type_80_1 : 4,
ru_type_80_0 : 4,
ldpc : 1,
sta_dcm : 1,
stream_offset : 3,
nss : 3,
qam_diff3 : 2,
qam_diff2 : 2,
qam_diff1 : 2,
reserved_2a : 1,
dl_ofdma_content_channel : 1;
uint32_t reserved_3d : 2,
ru_start_index_80_3 : 6,
reserved_3c : 2,
ru_start_index_80_2 : 6,
reserved_3b : 2,
ru_start_index_80_1 : 6,
reserved_3a : 2,
ru_start_index_80_0 : 6;
uint32_t user_fd_rssi_seg0 : 32;
uint32_t user_fd_rssi_seg1 : 32;
uint32_t user_fd_rssi_seg2 : 32;
uint32_t user_fd_rssi_seg3 : 32;
#endif
};
#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000
#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff
#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000
#define RECEIVE_USER_INFO_USER_RSSI_LSB 16
#define RECEIVE_USER_INFO_USER_RSSI_MSB 23
#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000
#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000
#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24
#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27
#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000
#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000
#define RECEIVE_USER_INFO_STBC_LSB 28
#define RECEIVE_USER_INFO_STBC_MSB 28
#define RECEIVE_USER_INFO_STBC_MASK 0x10000000
#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000
#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000
#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RATE_MCS_LSB 0
#define RECEIVE_USER_INFO_RATE_MCS_MSB 4
#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000001f
#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004
#define RECEIVE_USER_INFO_SGI_LSB 5
#define RECEIVE_USER_INFO_SGI_MSB 6
#define RECEIVE_USER_INFO_SGI_MASK 0x00000060
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000
#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19
#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23
#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1
#define RECEIVE_USER_INFO_RESERVED_2A_MSB 1
#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x00000002
#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET 0x00000008
#define RECEIVE_USER_INFO_QAM_DIFF1_LSB 2
#define RECEIVE_USER_INFO_QAM_DIFF1_MSB 3
#define RECEIVE_USER_INFO_QAM_DIFF1_MASK 0x0000000c
#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET 0x00000008
#define RECEIVE_USER_INFO_QAM_DIFF2_LSB 4
#define RECEIVE_USER_INFO_QAM_DIFF2_MSB 5
#define RECEIVE_USER_INFO_QAM_DIFF2_MASK 0x00000030
#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET 0x00000008
#define RECEIVE_USER_INFO_QAM_DIFF3_LSB 6
#define RECEIVE_USER_INFO_QAM_DIFF3_MSB 7
#define RECEIVE_USER_INFO_QAM_DIFF3_MASK 0x000000c0
#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008
#define RECEIVE_USER_INFO_NSS_LSB 8
#define RECEIVE_USER_INFO_NSS_MSB 10
#define RECEIVE_USER_INFO_NSS_MASK 0x00000700
#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008
#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11
#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13
#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800
#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008
#define RECEIVE_USER_INFO_STA_DCM_LSB 14
#define RECEIVE_USER_INFO_STA_DCM_MSB 14
#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000
#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008
#define RECEIVE_USER_INFO_LDPC_LSB 15
#define RECEIVE_USER_INFO_LDPC_MSB 15
#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000
#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000
#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000
#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000
#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f
#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6
#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7
#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00
#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14
#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15
#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000
#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22
#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23
#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000
#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30
#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31
#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RECEIVED_RESPONSE_USER_36_32_H_
#define _RECEIVED_RESPONSE_USER_36_32_H_
#include "received_response_user_info.h"
#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40
#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20
struct received_response_user_36_32 {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct received_response_user_info received_response_details_user32;
struct received_response_user_info received_response_details_user33;
struct received_response_user_info received_response_details_user34;
struct received_response_user_info received_response_details_user35;
struct received_response_user_info received_response_details_user36;
#else
struct received_response_user_info received_response_details_user32;
struct received_response_user_info received_response_details_user33;
struct received_response_user_info received_response_details_user34;
struct received_response_user_info received_response_details_user35;
struct received_response_user_info received_response_details_user36;
#endif
};
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
#define _RECEIVED_RESPONSE_USER_INFO_H_
#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
struct received_response_user_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t mpdu_fcs_pass_count : 12,
mpdu_fcs_fail_count : 12,
qosnull_frame_count : 4,
reserved_0a : 3,
user_info_valid : 1;
uint32_t null_delimiter_count : 22,
reserved_1a : 9,
ht_control_valid : 1;
uint32_t ht_control : 32;
uint32_t qos_control_valid : 16,
eosp : 16;
uint32_t qos_control_15_8_tid_0 : 8,
qos_control_15_8_tid_1 : 8,
qos_control_15_8_tid_2 : 8,
qos_control_15_8_tid_3 : 8;
uint32_t qos_control_15_8_tid_4 : 8,
qos_control_15_8_tid_5 : 8,
qos_control_15_8_tid_6 : 8,
qos_control_15_8_tid_7 : 8;
uint32_t qos_control_15_8_tid_8 : 8,
qos_control_15_8_tid_9 : 8,
qos_control_15_8_tid_10 : 8,
qos_control_15_8_tid_11 : 8;
uint32_t qos_control_15_8_tid_12 : 8,
qos_control_15_8_tid_13 : 8,
qos_control_15_8_tid_14 : 8,
qos_control_15_8_tid_15 : 8;
#else
uint32_t user_info_valid : 1,
reserved_0a : 3,
qosnull_frame_count : 4,
mpdu_fcs_fail_count : 12,
mpdu_fcs_pass_count : 12;
uint32_t ht_control_valid : 1,
reserved_1a : 9,
null_delimiter_count : 22;
uint32_t ht_control : 32;
uint32_t eosp : 16,
qos_control_valid : 16;
uint32_t qos_control_15_8_tid_3 : 8,
qos_control_15_8_tid_2 : 8,
qos_control_15_8_tid_1 : 8,
qos_control_15_8_tid_0 : 8;
uint32_t qos_control_15_8_tid_7 : 8,
qos_control_15_8_tid_6 : 8,
qos_control_15_8_tid_5 : 8,
qos_control_15_8_tid_4 : 8;
uint32_t qos_control_15_8_tid_11 : 8,
qos_control_15_8_tid_10 : 8,
qos_control_15_8_tid_9 : 8,
qos_control_15_8_tid_8 : 8;
uint32_t qos_control_15_8_tid_15 : 8,
qos_control_15_8_tid_14 : 8,
qos_control_15_8_tid_13 : 8,
qos_control_15_8_tid_12 : 8;
#endif
};
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff
#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c
#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16
#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31
#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RECEIVED_TRIGGER_INFO_H_
#define _RECEIVED_TRIGGER_INFO_H_
#include "received_trigger_info_details.h"
#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6
#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3
struct received_trigger_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct received_trigger_info_details received_trigger_details;
#else
struct received_trigger_info_details received_trigger_details;
#endif
};
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x0000000060000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB 61
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB 61
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK 0x2000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 62
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 62
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x4000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 63
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0x8000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 62
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xc000000000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET 0x0000000000000010
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB 40
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB 63
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK 0xffffff0000000000
#endif

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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6
struct received_trigger_info_details {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t trigger_type : 4,
ax_trigger_source : 1,
ax_trigger_type : 4,
trigger_source_sta_full_aid : 13,
frame_control_valid : 1,
qos_control_valid : 1,
he_control_info_valid : 1,
__reserved_g_0005_trigger_subtype : 4,
txop_sharing_mode : 2,
tid_aggregation_limit_is_zero : 1;
uint32_t phy_ppdu_id : 16,
lsig_response_length : 12,
__reserved_g_0086 : 1,
scsid_valid : 1,
ects_as_tb_ppdu : 1,
reserved_1a : 1;
uint32_t frame_control : 16,
qos_control : 16;
uint32_t sw_peer_id : 16,
txop_sharing_allocation_duration : 9,
__reserved_g_0074 : 4,
__reserved_g_0034 : 1,
reserved_3a : 2;
uint32_t he_control : 32;
uint32_t txop_sharing_duration_from_durid : 1,
frame_durationid_lower_4 : 4,
frame_durationid_upper_3 : 3,
reserved_5a : 24;
#else
uint32_t tid_aggregation_limit_is_zero : 1,
txop_sharing_mode : 2,
__reserved_g_0005_trigger_subtype : 4,
he_control_info_valid : 1,
qos_control_valid : 1,
frame_control_valid : 1,
trigger_source_sta_full_aid : 13,
ax_trigger_type : 4,
ax_trigger_source : 1,
trigger_type : 4;
uint32_t reserved_1a : 1,
ects_as_tb_ppdu : 1,
scsid_valid : 1,
__reserved_g_0086 : 1,
lsig_response_length : 12,
phy_ppdu_id : 16;
uint32_t qos_control : 16,
frame_control : 16;
uint32_t reserved_3a : 2,
__reserved_g_0034 : 1,
__reserved_g_0074 : 4,
txop_sharing_allocation_duration : 9,
sw_peer_id : 16;
uint32_t he_control : 32;
uint32_t reserved_5a : 24,
frame_durationid_upper_3 : 3,
frame_durationid_lower_4 : 4,
txop_sharing_duration_from_durid : 1;
#endif
};
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000
#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000
#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000
#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET 0x00000004
#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB 29
#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB 29
#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK 0x20000000
#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x00000004
#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB 30
#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB 30
#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK 0x40000000
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 31
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0x80000000
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 30
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xc0000000
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x00000014
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 0
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 0
#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x00000001
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x00000014
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 1
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 4
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x00000014
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 5
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 7
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e0
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET 0x00000014
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB 8
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB 31
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK 0xffffff00
#endif

305
hw/wcn8750/v1/reo_destination_ring.h Normal file
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@ -0,0 +1,305 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_DESTINATION_RING_H_
#define _REO_DESTINATION_RING_H_
#include "rx_msdu_desc_info.h"
#include "rx_mpdu_desc_info.h"
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_REO_DESTINATION_RING 8
struct reo_destination_ring {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info;
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t release_source_module : 3,
cookie_conversion_status : 1,
rxdma_push_reason : 2,
rxdma_error_code : 5,
reo_delink_error : 1,
sw_buffer_cookie : 20;
uint32_t msdu_link_desc_index : 4,
reserved_6a : 28;
uint32_t reo_dest_buffer_type : 1,
reo_push_reason : 2,
reo_error_code : 5,
captured_msdu_data_size : 4,
sw_exception : 1,
src_link_id : 3,
reo_destination_struct_signature : 4,
ring_id : 8,
looping_count : 4;
#else
struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info;
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t sw_buffer_cookie : 20,
reo_delink_error : 1,
rxdma_error_code : 5,
rxdma_push_reason : 2,
cookie_conversion_status : 1,
release_source_module : 3;
uint32_t reserved_6a : 28,
msdu_link_desc_index : 4;
uint32_t looping_count : 4,
ring_id : 8,
reo_destination_struct_signature : 4,
src_link_id : 3,
sw_exception : 1,
captured_msdu_data_size : 4,
reo_error_code : 5,
reo_push_reason : 2,
reo_dest_buffer_type : 1;
#endif
};
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000014
#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB 0
#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB 2
#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007
#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014
#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB 3
#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB 3
#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK 0x00000008
#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET 0x00000014
#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB 4
#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB 5
#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK 0x00000030
#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET 0x00000014
#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB 6
#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB 10
#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK 0x000007c0
#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET 0x00000014
#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB 11
#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB 11
#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK 0x00000800
#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET 0x00000014
#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB 12
#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB 31
#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018
#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB 0
#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB 3
#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK 0x0000000f
#define REO_DESTINATION_RING_RESERVED_6A_OFFSET 0x00000018
#define REO_DESTINATION_RING_RESERVED_6A_LSB 4
#define REO_DESTINATION_RING_RESERVED_6A_MSB 31
#define REO_DESTINATION_RING_RESERVED_6A_MASK 0xfffffff0
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001
#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1
#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2
#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006
#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3
#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7
#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00
#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c
#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12
#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12
#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000
#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13
#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15
#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000
#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_RING_ID_LSB 20
#define REO_DESTINATION_RING_RING_ID_MSB 27
#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000
#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28
#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31
#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
#endif

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hw/wcn8750/v1/reo_destination_ring_with_pn.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_DESTINATION_RING_WITH_PN_H_
#define _REO_DESTINATION_RING_WITH_PN_H_
#include "rx_msdu_desc_info.h"
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8
struct reo_destination_ring_with_pn {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info;
uint32_t msdu_count : 8,
prev_pn_23_0 : 24;
uint32_t prev_pn_47_24 : 24,
prev_pn_127_48_info : 2,
reserved_3a : 6;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t release_source_module : 3,
cookie_conversion_status : 1,
rxdma_push_reason : 2,
rxdma_error_code : 5,
reo_delink_error : 1,
sw_buffer_cookie : 20;
uint32_t msdu_link_desc_index : 4,
reserved_6a : 28;
uint32_t reo_dest_buffer_type : 1,
reo_push_reason : 2,
reo_error_code : 5,
captured_msdu_data_size : 4,
sw_exception : 1,
src_link_id : 3,
reo_destination_struct_signature : 4,
ring_id : 8,
looping_count : 4;
#else
struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info;
uint32_t prev_pn_23_0 : 24,
msdu_count : 8;
uint32_t reserved_3a : 6,
prev_pn_127_48_info : 2,
prev_pn_47_24 : 24;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t sw_buffer_cookie : 20,
reo_delink_error : 1,
rxdma_error_code : 5,
rxdma_push_reason : 2,
cookie_conversion_status : 1,
release_source_module : 3;
uint32_t reserved_6a : 28,
msdu_link_desc_index : 4;
uint32_t looping_count : 4,
ring_id : 8,
reo_destination_struct_signature : 4,
src_link_id : 3,
sw_exception : 1,
captured_msdu_data_size : 4,
reo_error_code : 5,
reo_push_reason : 2,
reo_dest_buffer_type : 1;
#endif
};
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET 0x0000000c
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB 0
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB 23
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK 0x00ffffff
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET 0x0000000c
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB 24
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB 25
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK 0x03000000
#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET 0x0000000c
#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB 26
#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB 31
#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK 0xfc000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET 0x00000014
#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB 0
#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB 2
#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK 0x00000007
#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014
#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB 3
#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB 3
#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK 0x00000008
#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET 0x00000014
#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB 4
#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB 5
#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK 0x00000030
#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET 0x00000014
#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB 6
#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB 10
#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK 0x000007c0
#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET 0x00000014
#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB 11
#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB 11
#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK 0x00000800
#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET 0x00000014
#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB 12
#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB 31
#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018
#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB 0
#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB 3
#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK 0x0000000f
#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET 0x00000018
#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB 4
#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB 31
#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK 0xfffffff0
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000
#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20
#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27
#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000
#endif

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hw/wcn8750/v1/reo_entrance_ring.h Normal file
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_ENTRANCE_RING_H_
#define _REO_ENTRANCE_RING_H_
#include "rx_mpdu_details.h"
#define NUM_OF_DWORDS_REO_ENTRANCE_RING 12
struct reo_entrance_ring {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct rx_mpdu_details reo_level_mpdu_frame_info;
uint32_t rx_preamble_timestamp : 32;
uint32_t reserved_7a : 8,
rounded_mpdu_byte_count : 14,
reo_destination_indication : 5,
frameless_bar : 1,
reserved_7b : 4;
uint32_t rxdma_push_reason : 2,
rxdma_error_code : 5,
mpdu_fragment_number : 4,
sw_exception : 1,
sw_exception_mpdu_delink : 1,
sw_exception_destination_ring_valid : 1,
sw_exception_destination_ring : 5,
mpdu_sequence_number : 12,
no_ack : 1;
uint32_t phy_ppdu_id : 16,
src_link_id : 3,
reserved_9a : 5,
rx_reo_queue_desc_addr_39_32 : 8;
uint32_t receive_queue_number : 16,
fw_reorder_push_reason : 2,
fw_reorder_error_code : 5,
reo_bypass : 1,
reserved_10a : 8;
uint32_t phy_lmac_latency : 16,
reserved_15a : 4,
ring_id : 8,
looping_count : 4;
#else
struct rx_mpdu_details reo_level_mpdu_frame_info;
uint32_t rx_preamble_timestamp : 32;
uint32_t reserved_7b : 4,
frameless_bar : 1,
reo_destination_indication : 5,
rounded_mpdu_byte_count : 14,
reserved_7a : 8;
uint32_t no_ack : 1,
mpdu_sequence_number : 12,
sw_exception_destination_ring : 5,
sw_exception_destination_ring_valid : 1,
sw_exception_mpdu_delink : 1,
sw_exception : 1,
mpdu_fragment_number : 4,
rxdma_error_code : 5,
rxdma_push_reason : 2;
uint32_t rx_reo_queue_desc_addr_39_32 : 8,
reserved_9a : 5,
src_link_id : 3,
phy_ppdu_id : 16;
uint32_t reserved_10a : 8,
reo_bypass : 1,
fw_reorder_error_code : 5,
fw_reorder_push_reason : 2,
receive_queue_number : 16;
uint32_t looping_count : 4,
ring_id : 8,
reserved_15a : 4,
phy_lmac_latency : 16;
#endif
};
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000
#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_OFFSET 0x00000018
#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_LSB 0
#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MSB 31
#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MASK 0xffffffff
#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_RESERVED_7A_LSB 0
#define REO_ENTRANCE_RING_RESERVED_7A_MSB 7
#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x000000ff
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000
#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27
#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27
#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000
#define REO_ENTRANCE_RING_RESERVED_7B_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_RESERVED_7B_LSB 28
#define REO_ENTRANCE_RING_RESERVED_7B_MSB 31
#define REO_ENTRANCE_RING_RESERVED_7B_MASK 0xf0000000
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000020
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000020
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000020
#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11
#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11
#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000020
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000020
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000020
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000
#define REO_ENTRANCE_RING_NO_ACK_OFFSET 0x00000020
#define REO_ENTRANCE_RING_NO_ACK_LSB 31
#define REO_ENTRANCE_RING_NO_ACK_MSB 31
#define REO_ENTRANCE_RING_NO_ACK_MASK 0x80000000
#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x00000024
#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0
#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15
#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff
#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x00000024
#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16
#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18
#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000
#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET 0x00000024
#define REO_ENTRANCE_RING_RESERVED_9A_LSB 19
#define REO_ENTRANCE_RING_RESERVED_9A_MSB 23
#define REO_ENTRANCE_RING_RESERVED_9A_MASK 0x00f80000
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000024
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 24
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 31
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0xff000000
#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000028
#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB 0
#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB 15
#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET 0x00000028
#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB 16
#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB 17
#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK 0x00030000
#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET 0x00000028
#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB 18
#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB 22
#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK 0x007c0000
#define REO_ENTRANCE_RING_REO_BYPASS_OFFSET 0x00000028
#define REO_ENTRANCE_RING_REO_BYPASS_LSB 23
#define REO_ENTRANCE_RING_REO_BYPASS_MSB 23
#define REO_ENTRANCE_RING_REO_BYPASS_MASK 0x00800000
#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET 0x00000028
#define REO_ENTRANCE_RING_RESERVED_10A_LSB 24
#define REO_ENTRANCE_RING_RESERVED_10A_MSB 31
#define REO_ENTRANCE_RING_RESERVED_10A_MASK 0xff000000
#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_OFFSET 0x0000002c
#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_LSB 0
#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MSB 15
#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MASK 0x0000ffff
#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET 0x0000002c
#define REO_ENTRANCE_RING_RESERVED_15A_LSB 16
#define REO_ENTRANCE_RING_RESERVED_15A_MSB 19
#define REO_ENTRANCE_RING_RESERVED_15A_MASK 0x000f0000
#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000002c
#define REO_ENTRANCE_RING_RING_ID_LSB 20
#define REO_ENTRANCE_RING_RING_ID_MSB 27
#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000
#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000002c
#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28
#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31
#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000
#endif

277
hw/wcn8750/v1/response_end_status.h Normal file
View file

@ -0,0 +1,277 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RESPONSE_END_STATUS_H_
#define _RESPONSE_END_STATUS_H_
#include "phytx_abort_request_info.h"
#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10
#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5
struct response_end_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t __reserved_g_0072 : 1,
__reserved_g_0065 : 1,
__reserved_g_0062 : 1,
global_data_underflow_warning : 1,
response_transmit_status : 4,
phytx_pkt_end_info_valid : 1,
phytx_abort_request_info_valid : 1,
generated_response : 3,
mba_user_count : 7,
mba_fake_bitmap_count : 7,
coex_based_tx_bw : 3,
trig_response_related : 1,
__reserved_g_0086 : 1;
struct phytx_abort_request_info phytx_abort_request_info_details;
uint16_t cbf_segment_request_mask : 8,
cbf_segment_sent_mask : 8;
uint32_t underflow_mpdu_count : 9,
data_underflow_warning : 2,
reserved_2b : 10,
only_null_delim_sent : 1,
brp_info_valid : 1,
__reserved_g_0067 : 1,
__reserved_g_0069 : 1,
__reserved_g_0051 : 1,
__reserved_g_0049 : 1,
__reserved_g_0047 : 1,
__reserved_g_0045 : 1,
__reserved_g_0043 : 1,
__reserved_g_0041 : 1,
__reserved_g_0030 : 1;
uint32_t mu_response_bitmap_31_0 : 32;
uint32_t mu_response_bitmap_36_32 : 5,
overwritten_blackout_window_bitmap : 4,
mic_overwritten : 1,
trig_resp_cmd_found : 1,
reserved_4a : 21;
uint32_t addr1_31_0 : 32;
uint32_t addr1_47_32 : 16,
addr2_15_0 : 16;
uint32_t addr2_47_16 : 32;
uint32_t addr3_31_0 : 32;
uint32_t addr3_47_32 : 16,
__reserved_g_0005 : 1,
secure : 1,
__reserved_g_0005_ftm_frame_sent : 1,
reserved_20a : 13;
#else
uint32_t __reserved_g_0086 : 1,
trig_response_related : 1,
coex_based_tx_bw : 3,
mba_fake_bitmap_count : 7,
mba_user_count : 7,
generated_response : 3,
phytx_abort_request_info_valid : 1,
phytx_pkt_end_info_valid : 1,
response_transmit_status : 4,
global_data_underflow_warning : 1,
__reserved_g_0062 : 1,
__reserved_g_0065 : 1,
__reserved_g_0072 : 1;
uint32_t cbf_segment_sent_mask : 8,
cbf_segment_request_mask : 8;
struct phytx_abort_request_info phytx_abort_request_info_details;
uint32_t __reserved_g_0030 : 1,
__reserved_g_0041 : 1,
__reserved_g_0043 : 1,
__reserved_g_0045 : 1,
__reserved_g_0047 : 1,
__reserved_g_0049 : 1,
__reserved_g_0051 : 1,
__reserved_g_0069 : 1,
__reserved_g_0067 : 1,
brp_info_valid : 1,
only_null_delim_sent : 1,
reserved_2b : 10,
data_underflow_warning : 2,
underflow_mpdu_count : 9;
uint32_t mu_response_bitmap_31_0 : 32;
uint32_t reserved_4a : 21,
trig_resp_cmd_found : 1,
mic_overwritten : 1,
overwritten_blackout_window_bitmap : 4,
mu_response_bitmap_36_32 : 5;
uint32_t addr1_31_0 : 32;
uint32_t addr2_15_0 : 16,
addr1_47_32 : 16;
uint32_t addr2_47_16 : 32;
uint32_t addr3_31_0 : 32;
uint32_t reserved_20a : 13,
__reserved_g_0005_ftm_frame_sent : 1,
secure : 1,
__reserved_g_0005 : 1,
addr3_47_32 : 16;
#endif
};
#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3
#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3
#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008
#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4
#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7
#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0
#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8
#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8
#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200
#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10
#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12
#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00
#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13
#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19
#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000
#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20
#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26
#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000
#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27
#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29
#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000
#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30
#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30
#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000
#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48
#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55
#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000
#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000
#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56
#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63
#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000
#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008
#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0
#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8
#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff
#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008
#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9
#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10
#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600
#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x0000000000000008
#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11
#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20
#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x00000000001ff800
#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008
#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21
#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21
#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000
#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008
#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22
#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22
#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f
#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET 0x0000000000000010
#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB 5
#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB 8
#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK 0x00000000000001e0
#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_OFFSET 0x0000000000000010
#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_LSB 9
#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MSB 9
#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MASK 0x0000000000000200
#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_OFFSET 0x0000000000000010
#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_LSB 10
#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MSB 10
#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MASK 0x0000000000000400
#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define RESPONSE_END_STATUS_RESERVED_4A_LSB 11
#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31
#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x00000000fffff800
#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000010
#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 32
#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 63
#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff00000000
#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000018
#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0
#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15
#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x000000000000ffff
#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000018
#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16
#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31
#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0x00000000ffff0000
#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000018
#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 32
#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 63
#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff00000000
#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000020
#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0
#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31
#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0x00000000ffffffff
#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000020
#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 32
#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 47
#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff00000000
#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000020
#define RESPONSE_END_STATUS_SECURE_LSB 49
#define RESPONSE_END_STATUS_SECURE_MSB 49
#define RESPONSE_END_STATUS_SECURE_MASK 0x0002000000000000
#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000020
#define RESPONSE_END_STATUS_RESERVED_20A_LSB 51
#define RESPONSE_END_STATUS_RESERVED_20A_MSB 63
#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff8000000000000
#endif

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