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msm: kgsl: Disable SP clock before enabling HWCG for holi
Holi has the GX power domain, Hence disable SP clock before programming any HWCG registers. Change-Id: I9007eb8b449e866a510d3713e0789c3b77d13887 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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1 changed files with 16 additions and 0 deletions
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@ -281,6 +281,18 @@ bool a6xx_cx_regulator_disable_wait(struct regulator *reg,
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}
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}
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static void set_holi_sptprac_clock(struct adreno_device *adreno_dev, bool enable)
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{
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u32 val = 0;
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adreno_read_gmu_wrapper(adreno_dev,
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A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, &val);
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val &= ~1;
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adreno_write_gmu_wrapper(adreno_dev,
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A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL,
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val | (enable ? 1 : 0));
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}
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static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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@ -320,6 +332,8 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on)
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!adreno_is_a610(adreno_dev))
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gmu_core_regrmw(device,
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A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
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else if (adreno_is_a619_holi(adreno_dev))
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set_holi_sptprac_clock(adreno_dev, false);
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for (i = 0; i < a6xx_core->hwcg_count; i++)
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kgsl_regwrite(device, a6xx_core->hwcg[i].offset,
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@ -334,6 +348,8 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on)
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!adreno_is_a610(adreno_dev))
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gmu_core_regrmw(device,
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A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
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else if (adreno_is_a619_holi(adreno_dev))
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set_holi_sptprac_clock(adreno_dev, true);
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/* enable top level HWCG */
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kgsl_regwrite(device, A6XX_RBBM_CLOCK_CNTL,
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