mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 05:39:54 -04:00
Merge "ARM: dts: msm: Add CSIPHY/CCI devicetree support for holi" into camera-kernel.lnx.4.0
This commit is contained in:
Haritha Chintalapati
Gerrit - the friendly Code Review server
commit
a3434cfaee
2 changed files with 288 additions and 1 deletions
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@ -17,7 +17,7 @@ First Level Node - CSIPHY device
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"qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1",
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"qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2",
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"qcom,csiphy-v1.2.3", "qcom,csiphy-v2.0.1", "qcom,csiphy-v2.1.0",
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"qcom,csiphy-v1.2.4", "qcom,csiphy".
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"qcom,csiphy-v1.2.4", "qcom,csiphy-v1.2.5", "qcom,csiphy".
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- cell-index: csiphy hardware core index
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Usage: required
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287
holi-camera.dtsi
287
holi-camera.dtsi
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@ -6,6 +6,293 @@
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status = "ok"
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};
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cam_csiphy0: qcom,csiphy0 {
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cell-index = <0>;
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compatible = "qcom,csiphy-v1.2.5", "qcom,csiphy";
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reg = <0x05C52000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0x52000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "mipi-csi-vdd1",
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"mipi-csi-vdd2";
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gdscr-supply = <&gcc_camss_top_gdsc>;
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mipi-csi-vdd1-supply = <&L18A>;
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mipi-csi-vdd2-supply = <&L22A>;
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 880000 1200000>;
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rgltr-max-voltage = <0 1049000 1305000>;
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rgltr-load-current = <0 0 15900 8900>;
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clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
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<&gcc GCC_CAMSS_CPHY_0_CLK>,
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<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>,
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<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy0_clk",
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"csi0phytimer_clk_src",
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"csi0phytimer_clk";
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src-clock-name = "csi0phytimer_clk_src";
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clock-cntl-level = "svs", "svs_l1", "nom", "turbo";
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clock-rates =
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<240000000 0 200000000 0>,
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<341330000 0 200000000 0>,
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<341330000 0 268800000 0>,
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<384000000 0 268800000 0>;
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status = "ok"
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};
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cam_csiphy1: qcom,csiphy1 {
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cell-index = <1>;
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compatible = "qcom,csiphy-v1.2.5", "qcom,csiphy";
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reg = <0x05C54000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0x54000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "mipi-csi-vdd1",
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"mipi-csi-vdd2";
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gdscr-supply = <&gcc_camss_top_gdsc>;
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mipi-csi-vdd1-supply = <&L18A>;
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mipi-csi-vdd2-supply = <&L22A>;
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 880000 1200000>;
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rgltr-max-voltage = <0 1049000 1305000>;
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rgltr-load-current = <0 15900 8900>;
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clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
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<&gcc GCC_CAMSS_CPHY_1_CLK>,
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<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>,
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<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy1_clk",
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"csi1phytimer_clk_src",
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"csi1phytimer_clk";
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src-clock-name = "csi1phytimer_clk_src";
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clock-cntl-level = "svs", "svs_l1", "nom", "turbo";
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clock-rates =
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<240000000 0 200000000 0>,
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<341330000 0 200000000 0>,
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<341330000 0 268800000 0>,
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<384000000 0 268800000 0>;
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status = "ok"
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};
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cam_csiphy2: qcom,csiphy2 {
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cell-index = <2>;
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compatible = "qcom,csiphy-v1.2.5", "qcom,csiphy";
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reg = <0x05C56000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0x56000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "mipi-csi-vdd1",
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"mipi-csi-vdd2";
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gdscr-supply = <&gcc_camss_top_gdsc>;
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mipi-csi-vdd1-supply = <&L18A>;
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mipi-csi-vdd2-supply = <&L22A>;
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 880000 1200000>;
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rgltr-max-voltage = <0 1049000 1305000>;
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rgltr-load-current = <0 15900 8900>;
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clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
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<&gcc GCC_CAMSS_CPHY_2_CLK>,
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<&gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>,
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<&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy2_clk",
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"csi2phytimer_clk_src",
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"csi2phytimer_clk";
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src-clock-name = "csi2phytimer_clk_src";
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clock-cntl-level = "svs", "svs_l1", "nom", "turbo";
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clock-rates =
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<240000000 0 200000000 0>,
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<341330000 0 200000000 0>,
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<341330000 0 268800000 0>,
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<384000000 0 268800000 0>;
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status = "ok"
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};
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cam_cci0: qcom,cci0 {
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cell-index = <0>;
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compatible = "qcom,cci";
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reg = <0x05C1B000 0x1000>;
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reg-names = "cci";
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reg-cam-base = <0x1B000>;
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interrupt-names = "cci";
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interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
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status = "ok"
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gdscr-supply = <&gcc_camss_top_gdsc>;
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regulator-names = "gdscr";
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clocks = <&gcc GCC_CAMSS_CCI_0_CLK>,
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<&gcc GCC_CAMSS_CCI_0_CLK_SRC>;
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clock-names = "cci_0_clk",
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"cci_0_clk_src";
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src-clock-name = "cci_0_clk_src";
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clock-cntl-level = "svs";
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clock-rates = <0 37500000>;
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pinctrl-names = "cam_default", "cam_suspend";
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pinctrl-0 = <&cci0_active &cci1_active>;
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pinctrl-1 = <&cci0_suspend &cci1_suspend>;
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gpios = <&tlmm 39 0>,
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<&tlmm 40 0>,
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<&tlmm 41 0>,
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<&tlmm 42 0>;
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gpio-req-tbl-num = <0 1 2 3>;
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gpio-req-tbl-flags = <1 1 1 1>;
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gpio-req-tbl-label = "CCI_I2C_DATA0",
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"CCI_I2C_CLK0",
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"CCI_I2C_DATA1",
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"CCI_I2C_CLK1";
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i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
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hw-thigh = <201>;
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hw-tlow = <174>;
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hw-tsu-sto = <204>;
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hw-tsu-sta = <231>;
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hw-thd-dat = <22>;
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hw-thd-sta = <162>;
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hw-tbuf = <227>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_custom_cci0: qcom,i2c_custom_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <1>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
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hw-thigh = <16>;
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hw-tlow = <22>;
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hw-tsu-sto = <17>;
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hw-tsu-sta = <18>;
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hw-thd-dat = <16>;
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hw-thd-sta = <15>;
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hw-tbuf = <24>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <3>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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};
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cam_cci1: qcom,cci1 {
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cell-index = <1>;
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compatible = "qcom,cci";
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reg = <0x05C1C000 0x1000>;
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reg-names = "cci";
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reg-cam-base = <0x1C000>;
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interrupt-names = "cci";
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interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
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status = "ok"
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gdscr-supply = <&gcc_camss_top_gdsc>;
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regulator-names = "gdscr";
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clocks = <&gcc GCC_CAMSS_CCI_1_CLK>,
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<&gcc GCC_CAMSS_CCI_1_CLK_SRC>;
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clock-names = "cci_1_clk",
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"cci_1_clk_src";
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src-clock-name = "cci_1_clk_src";
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clock-cntl-level = "svs";
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clock-rates = <0 37500000>;
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pinctrl-names = "cam_default", "cam_suspend";
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pinctrl-0 = <&cci2_active>;
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pinctrl-1 = <&cci2_suspend>;
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gpios = <&tlmm 43 0>,
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<&tlmm 44 0>;
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gpio-req-tbl-num = <0 1>;
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gpio-req-tbl-flags = <1 1>;
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gpio-req-tbl-label = "CCI_I2C_DATA2",
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"CCI_I2C_CLK2";
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i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
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hw-thigh = <201>;
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hw-tlow = <174>;
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hw-tsu-sto = <204>;
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hw-tsu-sta = <231>;
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hw-thd-dat = <22>;
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hw-thd-sta = <162>;
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hw-tbuf = <227>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_custom_cci1: qcom,i2c_custom_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <1>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
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hw-thigh = <16>;
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hw-tlow = <22>;
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hw-tsu-sto = <17>;
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hw-tsu-sta = <18>;
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hw-thd-dat = <16>;
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hw-thd-sta = <15>;
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hw-tbuf = <24>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <3>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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};
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qcom,cam-sync {
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compatible = "qcom,cam-sync";
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status = "ok"
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