From a34cb705aa6684f03a7fe1ce9d47d81e46bf15c4 Mon Sep 17 00:00:00 2001 From: liaohs Date: Thu, 27 Dec 2018 16:11:53 +0800 Subject: [PATCH] pmic: add power-off reason registers value add PMIC power-off reason registers' value : PON_POFF_REASON1 PON_OFF_REASON PON_FAULT_REASON1 PON_FAULT_REASON2 PON_S3_RESET_REASON Change-Id: I696dd9fbda3e6df111aa8282827fabea4260d297 Reviewed-on: https://gerrit.mot.com/1287551 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Haijian Ma Reviewed-by: Huosheng Liao Submit-Approved: Jira Key Reviewed-on: https://gerrit.mot.com/1470872 Reviewed-by: Zhenxin Xi Reviewed-on: https://gerrit.mot.com/1771184 --- drivers/input/misc/qpnp-power-on.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/input/misc/qpnp-power-on.c b/drivers/input/misc/qpnp-power-on.c index 49c00750dfe4..39255cd19086 100644 --- a/drivers/input/misc/qpnp-power-on.c +++ b/drivers/input/misc/qpnp-power-on.c @@ -2085,6 +2085,8 @@ static int qpnp_pon_read_gen2_pon_off_reason(struct qpnp_pon *pon, u16 *reason, rc = qpnp_pon_read(pon, QPNP_PON_OFF_REASON(pon), ®); if (rc) return rc; + dev_info(pon->dev, "PON Register , addr=0x%04X, val=0x%x\n", + QPNP_PON_OFF_REASON(pon), (u8)reg); if (reg & QPNP_GEN2_POFF_SEQ) { rc = qpnp_pon_read(pon, QPNP_POFF_REASON1(pon), ®1); @@ -2092,6 +2094,8 @@ static int qpnp_pon_read_gen2_pon_off_reason(struct qpnp_pon *pon, u16 *reason, return rc; *reason = (u8)reg1; *reason_index_offset = 0; + dev_info(pon->dev, "PON Register , addr=0x%04X, val=0x%x\n", + QPNP_POFF_REASON1(pon), (u8)buf[0]); } else if (reg & QPNP_GEN2_FAULT_SEQ) { rc = regmap_bulk_read(pon->regmap, QPNP_FAULT_REASON1(pon), buf, 2); @@ -2102,12 +2106,18 @@ static int qpnp_pon_read_gen2_pon_off_reason(struct qpnp_pon *pon, u16 *reason, } *reason = buf[0] | (u16)(buf[1] << 8); *reason_index_offset = POFF_REASON_FAULT_OFFSET; + dev_info(pon->dev, "PON Register , addr=0x%04X, val=0x%x\n", + QPNP_FAULT_REASON1(pon), (u8)buf[0]); + dev_info(pon->dev, "PON Register , addr=0x%04X, val=0x%x\n", + QPNP_FAULT_REASON1(pon), (u8)buf[1]); } else if (reg & QPNP_GEN2_S3_RESET_SEQ) { rc = qpnp_pon_read(pon, QPNP_S3_RESET_REASON(pon), ®1); if (rc) return rc; *reason = (u8)reg1; *reason_index_offset = POFF_REASON_S3_RESET_OFFSET; + dev_info(pon->dev, "PON Register , addr=0x%04X, val=0x%x\n", + QPNP_S3_RESET_REASON(pon), (u8)buf[0]); } return 0;