mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 15:49:17 -04:00
Merge "ARM: dts: msm: Add support for kgsl driver on SA8155"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
a3b322f713
4 changed files with 547 additions and 0 deletions
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@ -255,6 +255,74 @@
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0x0a44 0x03 0x0>;
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};
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/* GPU power level overrides */
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&msm_gpu {
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/delete-property/qcom,initial-pwrlevel;
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qcom,initial-pwrlevel = <4>;
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/delete-node/qcom,gpu-pwrlevels;
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/delete-node/qcom,gpu-pwrlevel-bins;
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qcom,gpu-pwrlevels {
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compatible = "qcom,gpu-pwrlevels";
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#address-cells = <1>;
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#size-cells = <0>;
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||||
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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||||
qcom,gpu-freq = <700000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <8>;
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qcom,bus-max = <11>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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||||
qcom,gpu-freq = <675000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <585000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <6>;
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qcom,bus-max = <11>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <500000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <6>;
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qcom,bus-max = <11>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <427000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <0>;
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qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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};
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&scc {
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compatible = "qcom,sa8155-scc-v2", "syscon";
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};
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276
qcom/sm8150-gpu.dtsi
Normal file
276
qcom/sm8150-gpu.dtsi
Normal file
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@ -0,0 +1,276 @@
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#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a640_zap";
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memory-region = <&pil_gpu_mem>;
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};
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msm_gpu: qcom,kgsl-3d0@2C00000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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status = "ok"
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reg = <0x2c00000 0x40000>, <0x2c61000 0x800>,
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<0x6900000 0x44000>, <0x780000 0x6fff>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc",
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"qdss_gfx", "qfprom_memory";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,chipid = <0x06040000>;
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qcom,initial-pwrlevel = <5>;
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qcom,gpu-quirk-secvid-set-once;
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qcom,gpu-quirk-cx-gdsc;
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qcom,idle-timeout = <80>; //msecs
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qcom,no-nap;
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qcom,highest-bank-bit = <15>;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <3>;
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qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size
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clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_AHB_CLK>;
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clock-names = "gcc_gpu_ahb", "rbbmtimer_clk",
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"gcc_gpu_axi_clk", "gcc_gpu_memnoc_gfx",
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"gmu_clk", "gpu_cc_ahb";
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qcom,isense-clk-on-level = <1>;
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-ddr =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(100, 4)>, /* index=1 */
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<MHZ_TO_KBPS(150, 4)>, /* index=2 */
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<MHZ_TO_KBPS(200, 4)>, /* index=3 */
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<MHZ_TO_KBPS(300, 4)>, /* index=4 */
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<MHZ_TO_KBPS(412, 4)>, /* index=5 */
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<MHZ_TO_KBPS(547, 4)>, /* index=6 */
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<MHZ_TO_KBPS(681, 4)>, /* index=7 */
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<MHZ_TO_KBPS(768, 4)>, /* index=8 */
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<MHZ_TO_KBPS(1017, 4)>, /* index=9 */
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<MHZ_TO_KBPS(1296, 4)>, /* index=10 */
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<MHZ_TO_KBPS(1555, 4)>, /* index=11 */
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<MHZ_TO_KBPS(1804, 4)>; /* index=12 */
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qcom,bus-table-cnoc =
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<0>, /* Off */
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<100>; /* On */
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/* GDSC regulator names */
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regulator-names = "vddcx", "vdd";
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/* GDSC oxili regulators */
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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qcom,l3-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,l3-pwrlevels";
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qcom,l3-pwrlevel@0 {
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reg = <0>;
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qcom,l3-freq = <0>;
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};
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qcom,l3-pwrlevel@1 {
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reg = <1>;
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qcom,l3-freq = <864000000>;
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};
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qcom,l3-pwrlevel@2 {
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reg = <2>;
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qcom,l3-freq = <1344000000>;
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};
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};
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/* GPU Mempools */
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-reserved = <2048>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-reserved = <1024>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
|
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};
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||||
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <600000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <12>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <553850000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <486460000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <379650000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <309110000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <5>;
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qcom,bus-max = <7>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <215000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
|
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <0>;
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qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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|
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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||||
qcom,bus-max = <0>;
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||||
};
|
||||
};
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|
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};
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|
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kgsl_msm_iommu: qcom,kgsl-iommu@0x02CA0000 {
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compatible = "qcom,kgsl-smmu-v2";
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|
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reg = <0x02CA0000 0x10000>;
|
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|
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gfx3d_user: gfx3d_user {
|
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compatible = "qcom,smmu-kgsl-cb";
|
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label = "gfx3d_user";
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iommus = <&kgsl_smmu 0x0 0x401>;
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qcom,iommu-dma = "disabled";
|
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};
|
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|
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gfx3d_secure: gfx3d_secure {
|
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compatible = "qcom,smmu-kgsl-cb";
|
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label = "gfx3d_secure";
|
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iommus = <&kgsl_smmu 0x2 0x400>;
|
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qcom,iommu-dma = "disabled";
|
||||
};
|
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};
|
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|
||||
gmu: qcom,gmu@0x2C6A000 {
|
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compatible = "qcom,gpu-gmu";
|
||||
|
||||
reg = <0x2c6a000 0x30000>,
|
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<0xb280000 0x10000>,
|
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<0xb480000 0x10000>;
|
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reg-names = "kgsl_gmu_reg",
|
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"kgsl_gmu_pdc_cfg",
|
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"kgsl_gmu_pdc_seq";
|
||||
|
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interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
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interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
|
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iommus = <&kgsl_smmu 0x5 0x400>;
|
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qcom,iommu-dma = "disabled";
|
||||
|
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vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
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<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
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"gcc_gpu_memnoc_gfx_clk", "gpu_cc_ahb";
|
||||
|
||||
/* AOP mailbox for sending ACD enable and disable messages */
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
|
||||
};
|
||||
};
|
||||
|
|
@ -296,3 +296,205 @@
|
|||
0x0a00 0x00 0x0
|
||||
0x0a44 0x03 0x0>;
|
||||
};
|
||||
|
||||
/* GPU overrides */
|
||||
&msm_gpu {
|
||||
/* Updated chip ID */
|
||||
qcom,chipid = <0x06040001>;
|
||||
|
||||
/* Power level to start throttling */
|
||||
qcom,throttle-pwrlevel = <0>;
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(300, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(1804, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(2092, 4)>; /* index=11 */
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
qcom,gpu-speed-bin = <0x4130 0xe0000000 29>;
|
||||
|
||||
/delete-property/qcom,initial-pwrlevel;
|
||||
/delete-node/qcom,gpu-pwrlevels;
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <585000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <499200000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <427000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <345000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <257000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <4>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <1>;
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <675000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <585000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <499200000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <427000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <345000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <257000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <4>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,l3-pwrlevels";
|
||||
|
||||
qcom,l3-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,l3-freq = <0>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,l3-freq = <1344000000>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,l3-freq = <1612800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmu {
|
||||
reg = <0x2c6a000 0x30000>,
|
||||
<0xb290000 0x10000>,
|
||||
<0xb490000 0x10000>;
|
||||
reg-names = "kgsl_gmu_reg",
|
||||
"kgsl_gmu_pdc_cfg",
|
||||
"kgsl_gmu_pdc_seq";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2401,3 +2401,4 @@
|
|||
};
|
||||
#include "sm8150-pcie.dtsi"
|
||||
#include "sm8150-usb.dtsi"
|
||||
#include "sm8150-gpu.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in a new issue