From a3df1c9115b513f13d3e5d52ca145a2dee4a2d14 Mon Sep 17 00:00:00 2001 From: Nitesh Gupta Date: Mon, 26 Apr 2021 23:36:20 +0530 Subject: [PATCH] ARM: dts: msm: add MHI register space info for PCIe on SA8195 Add MHI register space information for PCIe so feature such as displaying ASPM stats is possible on SA8195. Change-Id: I2633a8be063dd10fe5128ae51d532cd5969f3bc3 --- qcom/sa8195p-pcie.dtsi | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/qcom/sa8195p-pcie.dtsi b/qcom/sa8195p-pcie.dtsi index c48ae1e75bc7..6b6e6575c891 100644 --- a/qcom/sa8195p-pcie.dtsi +++ b/qcom/sa8195p-pcie.dtsi @@ -12,10 +12,12 @@ <0x60001000 0x1000>, <0x60100000 0x100000>, <0x60200000 0x100000>, - <0x60300000 0x3d00000>; + <0x60300000 0x3d00000>, + <0x01c03000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars"; + "iatu", "conf", "io", "bars", + "mhi"; #address-cells = <3>; #size-cells = <2>; @@ -282,10 +284,12 @@ <0x68100000 0x100000>, <0x68200000 0x100000>, <0x68300000 0x3d00000>, - <0x01fec004 0x4>; + <0x01fec004 0x4>, + <0x01c13000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars", "tcsr"; + "iatu", "conf", "io", "bars", "tcsr", + "mhi"; #address-cells = <3>; #size-cells = <2>; @@ -590,10 +594,12 @@ <0x70100000 0x100000>, <0x70200000 0x100000>, <0x70300000 0x3d00000>, - <0x01fec004 0x4>; + <0x01fec004 0x4>, + <0x01c1b000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars", "tcsr"; + "iatu", "conf", "io", "bars", "tcsr", + "mhi"; #address-cells = <3>; #size-cells = <2>; @@ -897,10 +903,12 @@ <0x40001000 0x1000>, <0x40100000 0x100000>, <0x40200000 0x100000>, - <0x40300000 0x1fd00000>; + <0x40300000 0x1fd00000>, + <0x01c0b000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars"; + "iatu", "conf", "io", "bars", + "mhi"; #address-cells = <3>; #size-cells = <2>;