ARM: dts: msm: Add clk levels for icp in KONA & LITO

Add all supporting clk levels for icp_clk_src for KONA
and lito. Apart from src clock the rates for fast_ahb
are updated aswell. The change also defines the src clock
 for a5 node.

Change-Id: Ib49d91e6a00db75fa04c4ad3e135e7b12e76edae
This commit is contained in:
Karthik Anantha Ram 2019-07-12 11:03:54 -07:00 • committed by Mukund Madhusudan Atre
commit a41d46e25f
2 changed files with 14 additions and 4 deletions

View file

@ -1523,6 +1523,7 @@
"icp_ahb_clk",
"icp_clk_src",
"icp_clk";
src-clock-name = "icp_clk_src";
clocks =
<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_ICP_AHB_CLK>,
@ -1530,9 +1531,13 @@
<&clock_camcc CAM_CC_ICP_CLK>;
clock-rates =
<100000000 0 400000000 0>,
<200000000 0 480000000 0>,
<300000000 0 600000000 0>,
<400000000 0 600000000 0>,
<400000000 0 600000000 0>;
clock-cntl-level = "svs", "turbo";
clock-cntl-level = "lowsvs", "svs", "svs_l1",
"nominal", "turbo";
fw_name = "CAMERA_ICP.elf";
ubwc-ipe-fetch-cfg = <0x707b 0x7083>;
ubwc-ipe-write-cfg = <0x161ef 0x1620f>;

View file

@ -782,6 +782,7 @@
"icp_ahb_clk",
"icp_clk_src",
"icp_clk";
src-clock-name = "icp_clk_src";
clocks =
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&camcc CAM_CC_ICP_AHB_CLK>,
@ -789,9 +790,13 @@
<&camcc CAM_CC_ICP_CLK>;
clock-rates =
<200000000 0 400000000 0>,
<300000000 0 600000000 0>;
clock-cntl-level = "svs", "svs_l1";
<100000000 0 400000000 0>,
<200000000 0 480000000 0>,
<300000000 0 600000000 0>,
<400000000 0 600000000 0>,
<400000000 0 600000000 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1",
"nominal", "turbo";
fw_name = "CAMERA_ICP.elf";
ubwc-cfg = <0x1073 0x101CF>;
qos-val = <0x00000A0A>;