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Merge "ARM: dts: msm: add dispcc clock reference for holi dsi-dsiplay node"

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qctecmdr 2021-12-22 07:12:37 -08:00 • committed by Gerrit - the friendly Code Review server
commit a41df1da24
1 changed files with 19 additions and 2 deletions
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21
display/holi-sde-display.dtsi
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@ -1,4 +1,5 @@
#include "holi-sde-display-common.dtsi"
#include <dt-bindings/clock/qcom,dispcc-holi.h>
&sde_dsi {
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
@ -6,10 +7,26 @@
<&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>;
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
"shadow_byte_clk0", "shadow_pixel_clk0",
"mdp_core_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_te_active &disp_pins_default>;