From 6a0f0b0f1fc404bcf769078991f65ab26ce85f76 Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Thu, 28 Apr 2022 00:40:30 +0530 Subject: [PATCH 1/3] disp: msm: sde: disable dsi ctrl regulator during deepsleep Disable DSI ctrl regulator while entering deepsleep and restore during resume. Refactor deepsleep related code to helper function. Change-Id: If6da0471db59fbdfa9d9855ee1464fcab90cae15 Signed-off-by: Venkata Prahlad Valluru Signed-off-by: Sai Srujana Oruganti --- msm/dsi/dsi_display.c | 60 +++++++++++++++++++++++++++++++++++++++++++ msm/dsi/dsi_display.h | 18 +++++++++++++ msm/sde/sde_kms.c | 54 +++++++++++++++++++++++--------------- 3 files changed, 111 insertions(+), 21 deletions(-) diff --git a/msm/dsi/dsi_display.c b/msm/dsi/dsi_display.c index 255ce9e0cca5..3e10738546bc 100644 --- a/msm/dsi/dsi_display.c +++ b/msm/dsi/dsi_display.c @@ -2455,6 +2455,63 @@ void dsi_display_enable_event(struct drm_connector *connector, } } +int dsi_display_ctrl_vreg_on(struct dsi_display *display) +{ + int rc = 0; + int i; + struct dsi_display_ctrl *ctrl; + struct dsi_ctrl *dsi_ctrl; + + display_for_each_ctrl(i, display) { + ctrl = &display->ctrl[i]; + if (!ctrl->ctrl) + continue; + + dsi_ctrl = ctrl->ctrl; + if (dsi_ctrl->current_state.host_initialized) { + rc = dsi_pwr_enable_regulator( + &dsi_ctrl->pwr_info.host_pwr, true); + if (rc) { + DSI_ERR("[%s] Failed to enable vreg, rc=%d\n", + dsi_ctrl->name, rc); + goto error; + } + DSI_DEBUG("[%s] Enable ctrl vreg\n", dsi_ctrl->name); + } + } +error: + return rc; +} + +int dsi_display_ctrl_vreg_off(struct dsi_display *display) +{ + int rc = 0; + int i; + struct dsi_display_ctrl *ctrl; + struct dsi_ctrl *dsi_ctrl; + + display_for_each_ctrl(i, display) { + ctrl = &display->ctrl[i]; + if (!ctrl->ctrl) + continue; + + dsi_ctrl = ctrl->ctrl; + if (dsi_ctrl->current_state.host_initialized) { + rc = dsi_pwr_enable_regulator( + &dsi_ctrl->pwr_info.host_pwr, false); + if (rc) { + DSI_ERR("[%s] Failed to disable vreg, rc=%d\n", + dsi_ctrl->name, rc); + goto error; + } + DSI_DEBUG("[%s] Disable ctrl vreg\n", dsi_ctrl->name); + } + } +error: + return rc; +} + + static int dsi_display_ctrl_power_on(struct dsi_display *display) { int rc = 0; @@ -4204,6 +4261,9 @@ static int dsi_display_parse_dt(struct dsi_display *display) display->needs_clk_src_reset = of_property_read_bool(of_node, "qcom,needs-clk-src-reset"); + display->needs_ctrl_vreg_disable = of_property_read_bool(of_node, + "qcom,needs-ctrl-vreg-disable"); + /* Parse all external bridges from port 0 */ display_for_each_ctrl(i, display) { display->ext_bridge[i].node_of = diff --git a/msm/dsi/dsi_display.h b/msm/dsi/dsi_display.h index cac84cd6a8a8..8724178e0541 100644 --- a/msm/dsi/dsi_display.h +++ b/msm/dsi/dsi_display.h @@ -215,6 +215,7 @@ struct dsi_display { bool is_te_irq_enabled; struct completion esd_te_gate; bool needs_clk_src_reset; + bool needs_ctrl_vreg_disable; u32 ctrl_count; struct dsi_display_ctrl ctrl[MAX_DSI_CTRLS_PER_DISPLAY]; @@ -817,4 +818,21 @@ int dsi_display_unset_clk_src(struct dsi_display *display); * Return: Zero on Success */ int dsi_display_set_clk_src(struct dsi_display *display); + +/** + * dsi_display_ctrl_vreg_on() - enable dsi ctrl regulator + * @display: Handle to display + * + * Return: Zero on Success + */ +int dsi_display_ctrl_vreg_on(struct dsi_display *display); + +/** + * dsi_display_ctrl_vreg_off() - disable dsi ctrl regulator + * @display: Handle to display + * + * Return: Zero on Success + */ +int dsi_display_ctrl_vreg_off(struct dsi_display *display); + #endif /* _DSI_DISPLAY_H_ */ diff --git a/msm/sde/sde_kms.c b/msm/sde/sde_kms.c index 9a11a6654f8f..e626561eba0d 100644 --- a/msm/sde/sde_kms.c +++ b/msm/sde/sde_kms.c @@ -3715,38 +3715,51 @@ void sde_kms_display_early_wakeup(struct drm_device *dev, } #ifdef CONFIG_DEEPSLEEP -static int _sde_kms_pm_set_clk_src(struct sde_kms *sde_kms, bool enable) +static int _sde_kms_pm_deepsleep_helper(struct sde_kms *sde_kms, bool enter) { int i, rc = 0; void *display; struct dsi_display *dsi_display; - if (mem_sleep_current == PM_SUSPEND_MEM) { - SDE_INFO("Deepsleep\n"); + if (mem_sleep_current != PM_SUSPEND_MEM) + return 0; - for (i = 0; i < sde_kms->dsi_display_count; i++) { - display = sde_kms->dsi_displays[i]; - dsi_display = (struct dsi_display *)display; + SDE_INFO("Deepsleep : enter %d\n", enter); - if (!dsi_display->needs_clk_src_reset) - continue; + for (i = 0; i < sde_kms->dsi_display_count; i++) { + display = sde_kms->dsi_displays[i]; + dsi_display = (struct dsi_display *)display; - if (enable) - rc = dsi_display_set_clk_src(dsi_display); - else - rc = dsi_display_unset_clk_src(dsi_display); - if (rc) { - SDE_ERROR("failed to set clks rc:%d\n", rc); - return rc; - } + if (enter) { + /* During deepsleep, clk_parent are reset at HW + * but sw caching is retained in clk framework. To + * maintain same state. unset parents and restore + * during exit. + */ + if (dsi_display->needs_clk_src_reset) + (void)dsi_display_unset_clk_src(dsi_display); + + /* DSI ctrl regulator can be disabled, even in static + * screen, during deepsleep + */ + if (dsi_display->needs_ctrl_vreg_disable) + (void)dsi_display_ctrl_vreg_off(dsi_display); + } else { + if (dsi_display->needs_ctrl_vreg_disable) + (void)dsi_display_ctrl_vreg_on(dsi_display); + + if (dsi_display->needs_clk_src_reset) + (void)dsi_display_set_clk_src(dsi_display); + } } return rc; } #else -static inline int _sde_kms_pm_set_clk_src(struct sde_kms *sde_kms, bool enable) +static inline int _sde_kms_pm_deepsleep_helper(struct sde_kms *sde_kms, + bool enter) { return 0; } @@ -3943,8 +3956,7 @@ unlock: pm_runtime_put_sync(dev); pm_runtime_get_noresume(dev); - /* reset clock source based on PM suspend state */ - _sde_kms_pm_set_clk_src(sde_kms, false); + _sde_kms_pm_deepsleep_helper(sde_kms, true); /* dump clock state before entering suspend */ if (sde_kms->pm_suspend_clk_dump) @@ -3983,8 +3995,8 @@ retry: goto end; } - /* reset clock source based on PM suspend state */ - _sde_kms_pm_set_clk_src(sde_kms, true); + /* If coming out of deepsleep, restore resources.*/ + _sde_kms_pm_deepsleep_helper(sde_kms, false); sde_kms->suspend_block = false; From a965033fba11266d97a84465a79c5ac63da296e5 Mon Sep 17 00:00:00 2001 From: Kai Xing Date: Wed, 18 May 2022 07:45:08 +0530 Subject: [PATCH 2/3] disp: msm: dsi: Add DSI PLL support for 7nm_v4_1 arch Add DSI PLL support for 7nm_v4_1 architecture Change-Id: I4adf1ec6ed40fea16aa80579d34a3c918faa8478 Signed-off-by: Kai Xing --- config/konadisp.conf | 1 + msm/dsi/dsi_pll.c | 5 +++++ msm/dsi/dsi_pll.h | 3 +++ msm/dsi/dsi_pll_5nm.c | 15 +++++++++++++-- 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/config/konadisp.conf b/config/konadisp.conf index dbbf3c847dbb..928706fee29f 100644 --- a/config/konadisp.conf +++ b/config/konadisp.conf @@ -11,3 +11,4 @@ export CONFIG_QCOM_MDSS_PLL=y export CONFIG_MSM_SDE_ROTATOR=y export CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y export CONFIG_DRM_SDE_RSC=y +export CONFIG_DISPLAY_BUILD=y diff --git a/msm/dsi/dsi_pll.c b/msm/dsi/dsi_pll.c index ce5d1cf3e245..5b310ca53378 100644 --- a/msm/dsi/dsi_pll.c +++ b/msm/dsi/dsi_pll.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ @@ -21,6 +23,7 @@ static int dsi_pll_clock_register(struct platform_device *pdev, switch (pll_res->pll_revision) { case DSI_PLL_5NM: + case DSI_PLL_7NM_V4_1: rc = dsi_pll_clock_register_5nm(pdev, pll_res); break; case DSI_PLL_10NM: @@ -150,6 +153,8 @@ int dsi_pll_init(struct platform_device *pdev, struct dsi_pll_resource **pll) if (!strcmp(label, "dsi_pll_5nm")) pll_res->pll_revision = DSI_PLL_5NM; + else if (!strcmp(label, "dsi_pll_7nm_v4_1")) + pll_res->pll_revision = DSI_PLL_7NM_V4_1; else if (!strcmp(label, "dsi_pll_10nm")) pll_res->pll_revision = DSI_PLL_10NM; else diff --git a/msm/dsi/dsi_pll.h b/msm/dsi/dsi_pll.h index 386fe6a93101..f424b8cb4843 100644 --- a/msm/dsi/dsi_pll.h +++ b/msm/dsi/dsi_pll.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ @@ -54,6 +56,7 @@ struct lpfr_cfg { enum { DSI_PLL_5NM, + DSI_PLL_7NM_V4_1, DSI_PLL_10NM, DSI_UNKNOWN_PLL, }; diff --git a/msm/dsi/dsi_pll_5nm.c b/msm/dsi/dsi_pll_5nm.c index f1c78cec1b22..501aa32b31ea 100644 --- a/msm/dsi/dsi_pll_5nm.c +++ b/msm/dsi/dsi_pll_5nm.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ @@ -291,6 +293,13 @@ static inline bool dsi_pll_5nm_is_hw_revision( true : false; } +static inline bool dsi_pll_7nm_v4_1_is_hw_revision( + struct dsi_pll_resource *rsc) +{ + return (rsc->pll_revision == DSI_PLL_7NM_V4_1) ? + true : false; +} + static inline int pll_reg_read(void *context, unsigned int reg, unsigned int *val) { @@ -2591,7 +2600,8 @@ int dsi_pll_clock_register_5nm(struct platform_device *pdev, dsi0pll_vco_clk.priv = pll_res; dsi0pll_shadow_vco_clk.priv = pll_res; - if (dsi_pll_5nm_is_hw_revision(pll_res)) { + if (dsi_pll_5nm_is_hw_revision(pll_res) || + dsi_pll_7nm_v4_1_is_hw_revision(pll_res)) { dsi0pll_vco_clk.min_rate = 600000000; dsi0pll_vco_clk.max_rate = 5000000000; dsi0pll_shadow_vco_clk.min_rate = 600000000; @@ -2660,7 +2670,8 @@ int dsi_pll_clock_register_5nm(struct platform_device *pdev, dsi1pll_vco_clk.priv = pll_res; dsi1pll_shadow_vco_clk.priv = pll_res; - if (dsi_pll_5nm_is_hw_revision(pll_res)) { + if (dsi_pll_5nm_is_hw_revision(pll_res) || + dsi_pll_7nm_v4_1_is_hw_revision(pll_res)) { dsi1pll_vco_clk.min_rate = 600000000; dsi1pll_vco_clk.max_rate = 5000000000; dsi1pll_shadow_vco_clk.min_rate = 600000000; From ed8c317940ac7643522ff5e68951a2835c924a1d Mon Sep 17 00:00:00 2001 From: Naresh Kumar Lingagalla Date: Thu, 7 Jul 2022 10:11:26 +0530 Subject: [PATCH 3/3] Revert "disp: msm: dsi: Add DSI PLL support for 7nm_v4_1 arch" This reverts commit a965033fba11266d97a84465a79c5ac63da296e5. Change-Id: Ifb3d9b1a10a28cd281459174a9291fea79ec781d Signed-off-by: Naresh Kumar Lingagalla --- config/konadisp.conf | 1 - msm/dsi/dsi_pll.c | 5 ----- msm/dsi/dsi_pll.h | 3 --- msm/dsi/dsi_pll_5nm.c | 15 ++------------- 4 files changed, 2 insertions(+), 22 deletions(-) diff --git a/config/konadisp.conf b/config/konadisp.conf index 928706fee29f..dbbf3c847dbb 100644 --- a/config/konadisp.conf +++ b/config/konadisp.conf @@ -11,4 +11,3 @@ export CONFIG_QCOM_MDSS_PLL=y export CONFIG_MSM_SDE_ROTATOR=y export CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y export CONFIG_DRM_SDE_RSC=y -export CONFIG_DISPLAY_BUILD=y diff --git a/msm/dsi/dsi_pll.c b/msm/dsi/dsi_pll.c index 5b310ca53378..ce5d1cf3e245 100644 --- a/msm/dsi/dsi_pll.c +++ b/msm/dsi/dsi_pll.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. - * * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ @@ -23,7 +21,6 @@ static int dsi_pll_clock_register(struct platform_device *pdev, switch (pll_res->pll_revision) { case DSI_PLL_5NM: - case DSI_PLL_7NM_V4_1: rc = dsi_pll_clock_register_5nm(pdev, pll_res); break; case DSI_PLL_10NM: @@ -153,8 +150,6 @@ int dsi_pll_init(struct platform_device *pdev, struct dsi_pll_resource **pll) if (!strcmp(label, "dsi_pll_5nm")) pll_res->pll_revision = DSI_PLL_5NM; - else if (!strcmp(label, "dsi_pll_7nm_v4_1")) - pll_res->pll_revision = DSI_PLL_7NM_V4_1; else if (!strcmp(label, "dsi_pll_10nm")) pll_res->pll_revision = DSI_PLL_10NM; else diff --git a/msm/dsi/dsi_pll.h b/msm/dsi/dsi_pll.h index f424b8cb4843..386fe6a93101 100644 --- a/msm/dsi/dsi_pll.h +++ b/msm/dsi/dsi_pll.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. - * * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ @@ -56,7 +54,6 @@ struct lpfr_cfg { enum { DSI_PLL_5NM, - DSI_PLL_7NM_V4_1, DSI_PLL_10NM, DSI_UNKNOWN_PLL, }; diff --git a/msm/dsi/dsi_pll_5nm.c b/msm/dsi/dsi_pll_5nm.c index 501aa32b31ea..f1c78cec1b22 100644 --- a/msm/dsi/dsi_pll_5nm.c +++ b/msm/dsi/dsi_pll_5nm.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. - * * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ @@ -293,13 +291,6 @@ static inline bool dsi_pll_5nm_is_hw_revision( true : false; } -static inline bool dsi_pll_7nm_v4_1_is_hw_revision( - struct dsi_pll_resource *rsc) -{ - return (rsc->pll_revision == DSI_PLL_7NM_V4_1) ? - true : false; -} - static inline int pll_reg_read(void *context, unsigned int reg, unsigned int *val) { @@ -2600,8 +2591,7 @@ int dsi_pll_clock_register_5nm(struct platform_device *pdev, dsi0pll_vco_clk.priv = pll_res; dsi0pll_shadow_vco_clk.priv = pll_res; - if (dsi_pll_5nm_is_hw_revision(pll_res) || - dsi_pll_7nm_v4_1_is_hw_revision(pll_res)) { + if (dsi_pll_5nm_is_hw_revision(pll_res)) { dsi0pll_vco_clk.min_rate = 600000000; dsi0pll_vco_clk.max_rate = 5000000000; dsi0pll_shadow_vco_clk.min_rate = 600000000; @@ -2670,8 +2660,7 @@ int dsi_pll_clock_register_5nm(struct platform_device *pdev, dsi1pll_vco_clk.priv = pll_res; dsi1pll_shadow_vco_clk.priv = pll_res; - if (dsi_pll_5nm_is_hw_revision(pll_res) || - dsi_pll_7nm_v4_1_is_hw_revision(pll_res)) { + if (dsi_pll_5nm_is_hw_revision(pll_res)) { dsi1pll_vco_clk.min_rate = 600000000; dsi1pll_vco_clk.max_rate = 5000000000; dsi1pll_shadow_vco_clk.min_rate = 600000000;