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cnss2: Update bound checks for sbl reg dumps to SRAM mem range

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Add code to update the bound checks for sbl reg dumps to SRAM mem
range. Due to a firmware update, the sbl start address was moved
and the bound checks to dumps sbl reg failed. Update the bound
checks to SRAM mem range, so that any future update in firmware
would not impact SRAM dumps.

Change-Id: I28026f03fe1f44f2ba6ff7f903dcb98543f8847c
Signed-off-by: Mohammed Siddiq <msiddiq@codeaurora.org>
This commit is contained in:
Mohammed Siddiq 2021-10-19 16:52:50 +05:30
commit a4946b539b
2 changed files with 11 additions and 20 deletions
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22
drivers/net/wireless/cnss2/pci.c
View file

@ -1493,9 +1493,9 @@ static void cnss_pci_dump_qca6390_sram_mem(struct cnss_pci_data *pci_priv)
sbl_log_size = (sbl_log_size > QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?
QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);
if (sbl_log_start < QCA6390_V2_SBL_DATA_START ||
sbl_log_start > QCA6390_V2_SBL_DATA_END ||
(sbl_log_start + sbl_log_size) > QCA6390_V2_SBL_DATA_END)
if (sbl_log_start < SRAM_START ||
sbl_log_start > SRAM_END ||
(sbl_log_start + sbl_log_size) > SRAM_END)
goto out;
cnss_pr_dbg("Dumping SBL log data\n");
@ -1563,17 +1563,11 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
sbl_log_size = (sbl_log_size > QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?
QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);
if (plat_priv->device_version.major_version == FW_V2_NUMBER) {
if (sbl_log_start < QCA6490_V2_SBL_DATA_START ||
sbl_log_start > QCA6490_V2_SBL_DATA_END ||
(sbl_log_start + sbl_log_size) > QCA6490_V2_SBL_DATA_END)
goto out;
} else {
if (sbl_log_start < QCA6490_V1_SBL_DATA_START ||
sbl_log_start > QCA6490_V1_SBL_DATA_END ||
(sbl_log_start + sbl_log_size) > QCA6490_V1_SBL_DATA_END)
goto out;
}
if (sbl_log_start < SRAM_START ||
sbl_log_start > SRAM_END ||
(sbl_log_start + sbl_log_size) > SRAM_END)
goto out;
cnss_pr_dbg("Dumping SBL log data\n");
for (i = 0; i < sbl_log_size; i += sizeof(val)) {

9
drivers/net/wireless/cnss2/reg.h
View file

@ -303,10 +303,6 @@
#define QCA6490_DEBUG_PBL_LOG_SRAM_START 0x01403DA0
#define QCA6490_DEBUG_PBL_LOG_SRAM_MAX_SIZE 40
#define QCA6490_V1_SBL_DATA_START 0x143b000
#define QCA6490_V1_SBL_DATA_END (0x143b000 + 0x00011000)
#define QCA6490_V2_SBL_DATA_START 0x1435000
#define QCA6490_V2_SBL_DATA_END (0x1435000 + 0x00011000)
#define QCA6490_DEBUG_SBL_LOG_SRAM_MAX_SIZE 48
#define QCA6490_TCSR_PBL_LOGGING_REG 0x01B000F8
#define QCA6490_PCIE_BHI_ERRDBG2_REG 0x01E0E238
@ -316,8 +312,6 @@
#define QCA6390_DEBUG_PBL_LOG_SRAM_START 0x01403D58
#define QCA6390_DEBUG_PBL_LOG_SRAM_MAX_SIZE 80
#define QCA6390_V2_SBL_DATA_START 0x016c8580
#define QCA6390_V2_SBL_DATA_END (0x016c8580 + 0x00011000)
#define QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE 44
#define QCA6390_TCSR_PBL_LOGGING_REG 0x01B000F8
#define QCA6390_PCIE_BHI_ERRDBG2_REG 0x01E0E238
@ -329,4 +323,7 @@
#define PCIE_SCRATCH_0_SOC_PCIE_REG 0x1E04040
#define PCIE_SCRATCH_1_SOC_PCIE_REG 0x1E04044
#define PCIE_SCRATCH_2_SOC_PCIE_REG 0x1E0405C
#define SRAM_START 0x01400000
#define SRAM_END 0x01800000
#endif