From 837a9194cee0f7242d2c70c40d6f7a6ce2d276be Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Tue, 11 Aug 2020 15:10:33 -0700 Subject: [PATCH 1/2] ARM: dts: msm: add display related SPMI address Add SPMI reference node along with the display related SPMI address. This will be used during the trusted-ui usecase where the VMs uses SPMI api to get the physical address, which will be lent/validated during the usecase. Change-Id: Ic3173410790443e87c0584681ec1f0c160fc04a2 --- bindings/sde.txt | 3 +++ display/lahaina-sde-common.dtsi | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 69430faef8d1..9fa9bfc70aba 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -528,6 +528,8 @@ Optional properties: should be excluded from IO memory validation list in trusted vm environment - qcom,vram-size: A u32 value indicating the size of the VRAM in bytes +- qcom,pmic-arb-address: A u32 array of display related SPMI address + bit mask, which is a combination of SID and pheripheral id's. Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -808,6 +810,7 @@ Example: qcom,sde-secure-sid-mask = <0x200801 0x200c01>; qcom,vram-size = <0x200000>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 738a141a3dc2..3730cc8d6dd7 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -228,6 +228,10 @@ qcom,sde-secure-sid-mask = <0x4000821>; + /* SPMI address related to display */ + qcom,pmic-arb = <&spmi_bus>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + qcom,sde-reg-bus,vectors-KBps = <0 0>, <0 74000>, <0 148000>, From ce3b61edb9c1b539c184f099dd9b13b1852a4628 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Tue, 11 Aug 2020 15:10:40 -0700 Subject: [PATCH 2/2] ARM: dts: msm: add gpio pins/address used for BOE cmd panel Add the TLMM base address & size of each GPIO register space along with all the GPIO pins used to drive the DSI host and the BOE panel. Change-Id: Ifabc0713de8c893fdd8b8a0fc38898898ec3c571 --- bindings/mdss-dsi-panel.txt | 9 +++++++++ display/lahaina-sde-display-common.dtsi | 3 +++ 2 files changed, 12 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index f6c67e5727cd..69bdd72ee00e 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -578,6 +578,11 @@ Optional properties: to identify the default topology for the display. The first set is indexed by the value 0. +- qcom,dsi-panel-gpio-address: An u32 pair consisting of base address of the + TLMM register space and size of each GPIO pin. +- qcom,dsi-panel-gpio-pins: An u32 array consisting of all the GPIO pins used + for driving the DSI host and the panels + connected to the host. - qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. - qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active region for video mode panels and line number after TE for command mode @@ -759,6 +764,10 @@ Example: qcom,mdss-dsi-force-clock-lane-hs; qcom,compression-mode = "dsc"; qcom,adjust-timer-wakeup-ms = <1>; + + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,mdss-dsi-display-timings { wqhd { qcom,mdss-dsi-cmd-mode; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 79bd533246cb..db0de1573d19 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -124,6 +124,9 @@ qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05