From a5284d9b5f66cd86a56ed3e85d6cecf020eec197 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 2 Sep 2020 12:36:50 +0530 Subject: [PATCH] ARM: dts: msm: create sde-common device tree for shima target Separate common SDE bindings in sde-common dt file so that unwanted duplications between VM variants of SDE files can be avoided. Change-Id: I78563c64f1b505e42669e6680fed64f85d513f25 --- display/shima-sde-common.dtsi | 389 ++++++++++++++++++++++++++ display/shima-sde.dtsi | 513 +++++----------------------------- 2 files changed, 463 insertions(+), 439 deletions(-) create mode 100644 display/shima-sde-common.dtsi diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi new file mode 100644 index 000000000000..a3a5861c05e4 --- /dev/null +++ b/display/shima-sde-common.dtsi @@ -0,0 +1,389 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + clock-rate = <0 0 0 0 460000000 19200000 460000000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none"; + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + + qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x84000 0x84100>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-pair-mask = <2 1>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + qcom,sde-sspp-xin-id = <0 4 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, + <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2880>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x7 0x1>, + <0x8 0x2>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <5900000>; + qcom,sde-max-bw-high-kbps = <13500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + /* creq LUTs */ + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-id = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801 0xC01>; + + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96400 0x800>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index e7a9fa86ef15..6e5e724c7e6e 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -1,274 +1,7 @@ +#include "shima-sde-common.dtsi" #include &soc { - mdss_mdp: qcom,mdss_mdp@ae00000 { - compatible = "qcom,sde-kms"; - reg = <0xae00000 0x84208>, - <0xaeb0000 0x2008>, - <0xaeac000 0x214>, - <0xaf50000 0x038>; - reg-names = "mdp_phys", - "vbif_phys", - "regdma_phys", - "swfuse_phys"; - clocks = - <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 0 0 460000000 19200000 460000000>; - clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - vdd-supply = <&disp_cc_mdss_core_gdsc>; - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; - qcom,sde-ctl-size = <0x1dc>; - qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; - - qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", "primary", "none", - "none"; - qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000 0x57000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-top-size = <0x1c>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-dest-scaler-size = <0x800>; - - qcom,sde-wb-off = <0x66000>; - qcom,sde-wb-size = <0x2c8>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-wb-clk-status = <0x3bc 20>; - - qcom,sde-intf-off = <0x6b000 0x6b800 - 0x6c000 0x6c800>; - qcom,sde-intf-size = <0x2b8>; - qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; - qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; - - qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; - qcom,sde-pp-size = <0xd4>; - qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; - - qcom,sde-merge-3d-off = <0x84000 0x84100>; - qcom,sde-merge-3d-size = <0x100>; - - qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; - - qcom,sde-cdm-off = <0x7a200>; - qcom,sde-cdm-size = <0x224>; - - qcom,sde-dsc-off = <0x81000 0x81400>; - qcom,sde-dsc-size = <0x140>; - qcom,sde-dsc-pair-mask = <2 1>; - - qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 - 0x30e0>; - qcom,sde-dither-version = <0x00010000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-sspp-type = "vig", "vig", - "dma", "dma", "dma"; - qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; - qcom,sde-sspp-src-size = <0x1f8>; - qcom,sde-sspp-xin-id = <0 4 1 5 9>; - qcom,sde-sspp-excl-rect = <1 1 1 1 1>; - qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <2 1 4 3>; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0>; - - qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, - <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; - qcom,sde-sspp-clk-status = - <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, - <0x2b8 12>, <0x2c8 12>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <2880>; - qcom,sde-vig-sspp-linewidth = <4096>; - qcom,sde-scaling-linewidth = <2560>; - qcom,sde-wb-linewidth = <4096>; - qcom,sde-mixer-blendstages = <0x9>; - qcom,sde-highest-bank-bit = <0x7 0x1>, - <0x8 0x2>; - qcom,sde-ubwc-version = <0x400>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1>; - qcom,sde-macrotile-mode = <0x1>; - qcom,sde-smart-panel-align-mode = <0xc>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-has-dest-scaler; - qcom,sde-has-idle-pc; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-max-bw-low-kbps = <5900000>; - qcom,sde-max-bw-high-kbps = <13500000>; - qcom,sde-min-core-ib-kbps = <2500000>; - qcom,sde-min-llcc-ib-kbps = <0>; - qcom,sde-min-dram-ib-kbps = <1600000>; - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-ltm-version = <0x00010000>; - /* offsets are based off dspp 0 and dspp 1 */ - qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x1040>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - - /* macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 - 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff - 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; - - qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, - <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; - - /* creq LUTs */ - qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; - qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; - qcom,sde-qos-refresh-rates = <60 120>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-id = <0>; - qcom,sde-reg-dma-version = <0x00010002>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - qcom,sde-secure-sid-mask = <0x801 0xC01>; - - /* data and reg bus scale settings */ - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 74000>, - <0 148000>, - <0 265000>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - qcom,sde-vig-inverse-pma; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - }; - - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - }; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040002>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - ext_disp: qcom,msm-ext-disp { status = "disabled"; compatible = "qcom,msm-ext-disp"; @@ -453,181 +186,83 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; +}; - mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-0"; - cell-index = <0>; - frame-threshold-time-us = <800>; - reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; +&mdss_mdp { + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + vdd-supply = <&disp_cc_mdss_core_gdsc>; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010000>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-1"; - cell-index = <1>; - frame-threshold-time-us = <800>; - reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <5 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-0"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-1"; - cell-index = <1>; - #clock-cells = <1>; - reg = <0xae96400 0x800>, - <0xae96900 0x27c>, - <0xaf03000 0x8>, - <0xae96200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; }; }; }; + +&mdss_dsi0 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +};