Merge branch 'asoc-5.2' into asoc-5.3

This commit is contained in:
Mark Brown 2019-06-03 18:38:15 +01:00
commit a529819d88
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GPG key ID: 24D68B725D5487D0
12 changed files with 115 additions and 38 deletions

View file

@ -48,6 +48,7 @@
#define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U)
#define SOF_IPC_GLB_DAI_MSG SOF_GLB_TYPE(0x8U)
#define SOF_IPC_GLB_TRACE_MSG SOF_GLB_TYPE(0x9U)
#define SOF_IPC_GLB_GDB_DEBUG SOF_GLB_TYPE(0xAU)
/*
* DSP Command Message Types
@ -78,6 +79,7 @@
#define SOF_IPC_COMP_GET_VALUE SOF_CMD_TYPE(0x002)
#define SOF_IPC_COMP_SET_DATA SOF_CMD_TYPE(0x003)
#define SOF_IPC_COMP_GET_DATA SOF_CMD_TYPE(0x004)
#define SOF_IPC_COMP_NOTIFICATION SOF_CMD_TYPE(0x005)
/* DAI messages */
#define SOF_IPC_DAI_CONFIG SOF_CMD_TYPE(0x001)
@ -153,6 +155,27 @@ struct sof_ipc_compound_hdr {
uint32_t count; /**< count of 0 means end of compound sequence */
} __packed;
/**
* OOPS header architecture specific data.
*/
struct sof_ipc_dsp_oops_arch_hdr {
uint32_t arch; /* Identifier of architecture */
uint32_t totalsize; /* Total size of oops message */
} __packed;
/**
* OOPS header platform specific data.
*/
struct sof_ipc_dsp_oops_plat_hdr {
uint32_t configidhi; /* ConfigID hi 32bits */
uint32_t configidlo; /* ConfigID lo 32bits */
uint32_t numaregs; /* Special regs num */
uint32_t stackoffset; /* Offset to stack pointer from beginning of
* oops message
*/
uint32_t stackptr; /* Stack ptr */
} __packed;
/** @}*/
#endif

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@ -18,6 +18,14 @@
#define SOF_IPC_MAX_ELEMS 16
/*
* Firmware boot info flag bits (64-bit)
*/
#define SOF_IPC_INFO_BUILD BIT(0)
#define SOF_IPC_INFO_LOCKS BIT(1)
#define SOF_IPC_INFO_LOCKSV BIT(2)
#define SOF_IPC_INFO_GDB BIT(3)
/* extended data types that can be appended onto end of sof_ipc_fw_ready */
enum sof_ipc_ext_data {
SOF_IPC_EXT_DMA_BUFFER = 0,
@ -49,16 +57,8 @@ struct sof_ipc_fw_ready {
uint32_t hostbox_size;
struct sof_ipc_fw_version version;
/* Miscellaneous debug flags showing build/debug features enabled */
union {
uint64_t reserved;
struct {
uint64_t build:1;
uint64_t locks:1;
uint64_t locks_verbose:1;
uint64_t gdb:1;
} bits;
} debug;
/* Miscellaneous flags */
uint64_t flags;
/* reserved for future use */
uint32_t reserved[4];

View file

@ -17,7 +17,8 @@
/* Xtensa Firmware Oops data */
struct sof_ipc_dsp_oops_xtensa {
struct sof_ipc_hdr hdr;
struct sof_ipc_dsp_oops_arch_hdr arch_hdr;
struct sof_ipc_dsp_oops_plat_hdr plat_hdr;
uint32_t exccause;
uint32_t excvaddr;
uint32_t ps;
@ -38,7 +39,11 @@ struct sof_ipc_dsp_oops_xtensa {
uint32_t intenable;
uint32_t interrupt;
uint32_t sar;
uint32_t stack;
uint32_t debugcause;
uint32_t windowbase;
uint32_t windowstart;
uint32_t excsave1;
uint32_t ar[];
} __packed;
#endif