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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
Merge branch 'asoc-5.2' into asoc-5.3
This commit is contained in:
commit
a529819d88
12 changed files with 115 additions and 38 deletions
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@ -48,6 +48,7 @@
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#define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U)
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#define SOF_IPC_GLB_DAI_MSG SOF_GLB_TYPE(0x8U)
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#define SOF_IPC_GLB_TRACE_MSG SOF_GLB_TYPE(0x9U)
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#define SOF_IPC_GLB_GDB_DEBUG SOF_GLB_TYPE(0xAU)
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/*
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* DSP Command Message Types
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@ -78,6 +79,7 @@
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#define SOF_IPC_COMP_GET_VALUE SOF_CMD_TYPE(0x002)
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#define SOF_IPC_COMP_SET_DATA SOF_CMD_TYPE(0x003)
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#define SOF_IPC_COMP_GET_DATA SOF_CMD_TYPE(0x004)
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#define SOF_IPC_COMP_NOTIFICATION SOF_CMD_TYPE(0x005)
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/* DAI messages */
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#define SOF_IPC_DAI_CONFIG SOF_CMD_TYPE(0x001)
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@ -153,6 +155,27 @@ struct sof_ipc_compound_hdr {
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uint32_t count; /**< count of 0 means end of compound sequence */
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} __packed;
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/**
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* OOPS header architecture specific data.
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*/
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struct sof_ipc_dsp_oops_arch_hdr {
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uint32_t arch; /* Identifier of architecture */
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uint32_t totalsize; /* Total size of oops message */
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} __packed;
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/**
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* OOPS header platform specific data.
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*/
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struct sof_ipc_dsp_oops_plat_hdr {
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uint32_t configidhi; /* ConfigID hi 32bits */
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uint32_t configidlo; /* ConfigID lo 32bits */
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uint32_t numaregs; /* Special regs num */
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uint32_t stackoffset; /* Offset to stack pointer from beginning of
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* oops message
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*/
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uint32_t stackptr; /* Stack ptr */
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} __packed;
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/** @}*/
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#endif
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@ -18,6 +18,14 @@
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#define SOF_IPC_MAX_ELEMS 16
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/*
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* Firmware boot info flag bits (64-bit)
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*/
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#define SOF_IPC_INFO_BUILD BIT(0)
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#define SOF_IPC_INFO_LOCKS BIT(1)
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#define SOF_IPC_INFO_LOCKSV BIT(2)
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#define SOF_IPC_INFO_GDB BIT(3)
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/* extended data types that can be appended onto end of sof_ipc_fw_ready */
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enum sof_ipc_ext_data {
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SOF_IPC_EXT_DMA_BUFFER = 0,
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@ -49,16 +57,8 @@ struct sof_ipc_fw_ready {
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uint32_t hostbox_size;
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struct sof_ipc_fw_version version;
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/* Miscellaneous debug flags showing build/debug features enabled */
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union {
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uint64_t reserved;
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struct {
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uint64_t build:1;
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uint64_t locks:1;
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uint64_t locks_verbose:1;
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uint64_t gdb:1;
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} bits;
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} debug;
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/* Miscellaneous flags */
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uint64_t flags;
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/* reserved for future use */
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uint32_t reserved[4];
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@ -17,7 +17,8 @@
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/* Xtensa Firmware Oops data */
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struct sof_ipc_dsp_oops_xtensa {
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struct sof_ipc_hdr hdr;
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struct sof_ipc_dsp_oops_arch_hdr arch_hdr;
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struct sof_ipc_dsp_oops_plat_hdr plat_hdr;
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uint32_t exccause;
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uint32_t excvaddr;
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uint32_t ps;
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@ -38,7 +39,11 @@ struct sof_ipc_dsp_oops_xtensa {
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uint32_t intenable;
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uint32_t interrupt;
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uint32_t sar;
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uint32_t stack;
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uint32_t debugcause;
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uint32_t windowbase;
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uint32_t windowstart;
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uint32_t excsave1;
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uint32_t ar[];
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} __packed;
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#endif
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