From 1b05249e4879860099026478c4d9fc898caa0b0c Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Thu, 23 Jul 2020 03:58:09 +0530 Subject: [PATCH] phy: ufs: Add UFS PHY support for Holi This change adds ufs phy support for Holi. Change-Id: I0d859b0371ca9402e7040ffc0a647657cf67e1e0 Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/Kconfig | 6 ++++++ drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c | 11 +++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 667cfd74298d..39ba3473a76f 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -89,6 +89,12 @@ config PHY_QCOM_UFS_QRBTC_SDM845 No low power mode support is present. Doesn't restrict number of lanes. +config PHY_QCOM_UFS_V3 + tristate + default PHY_QCOM_UFS + help + Support for 8nm UFS QMP phy present on QCOM chipsets. + endif config PHY_QCOM_USB_HS diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c index 0ec139c165b1..668a08e32f4b 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c @@ -50,17 +50,20 @@ static int ufs_qcom_phy_qmp_v3_phy_calibrate(struct phy *generic_phy) phy_cal_table_2nd_lane, ARRAY_SIZE(phy_cal_table_2nd_lane)); } else { - ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_no_g4, - ARRAY_SIZE(phy_cal_table_rate_A_no_g4)); + ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A, + ARRAY_SIZE(phy_cal_table_rate_A)); if (ufs_qcom_phy->lanes_per_direction == 2) ufs_qcom_phy_write_tbl(ufs_qcom_phy, - phy_cal_table_2nd_lane_no_g4, - ARRAY_SIZE(phy_cal_table_2nd_lane_no_g4)); + phy_cal_table_2nd_lane, + ARRAY_SIZE(phy_cal_table_2nd_lane)); } if (is_rate_B) ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B, ARRAY_SIZE(phy_cal_table_rate_B)); + /* flush buffered writes */ + mb(); + err = reset_control_deassert(ufs_qcom_phy->ufs_reset); if (err) { dev_err(dev, "Failed to deassert UFS PHY reset %d\n", err);