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PCI: imx6: Add DT property for link gen, default to Gen1

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Freescale has stated [1] that the LVDS clock source of the IMX6 does not
pass the PCI Gen2 clock jitter test, therefore unless an external Gen2
compliant external clock source is present and supplied back to the IMX6
PCIe core via LVDS CLK1/CLK2 you can not claim Gen2 compliance.

Add a DT property to specify Gen1 vs Gen2 and check this before allowing a
Gen2 link.

We default to Gen1 if the property is not present because at this time
there are no IMX6 boards in mainline that 'input' a clock on LVDS
CLK1/CLK2.

In order to be Gen2 compliant on IMX6 you need to:

 - Have a Gen2 compliant external clock generator and route that clock back
   to either LVDS CLK1 or LVDS CLK2 as an input (see IMX6SX-SabreSD
   reference design).

 - Specify this clock in the PCIe node in the DT (i.e.,
   IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of
   IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output).

[1] https://community.freescale.com/message/453209

Signed-off-by: Tim Harvey <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
CC: Fabio Estevam <[email protected]>
CC: Zhu Richard <[email protected]>
CC: Akshay Bhat <[email protected]>
CC: Rob Herring <[email protected]>
CC: Shawn Guo <[email protected]>
This commit is contained in:
Tim Harvey 2016-04-19 19:52:44 -05:00 • committed by Bjorn Helgaas
commit a5fcec480f
2 changed files with 21 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

24
drivers/pci/host/pci-imx6.c
View file

@ -47,6 +47,7 @@ struct imx6_pcie {
u32 tx_deemph_gen2_6db;
u32 tx_swing_full;
u32 tx_swing_low;
int link_gen;
};
/* PCIe Root Complex registers (memory-mapped) */
@ -471,11 +472,15 @@ static int imx6_pcie_establish_link(struct pcie_port *pp)
goto err_reset_phy;
}
/* Allow Gen2 mode after the link is up. */
tmp = readl(pp->dbi_base + PCIE_RC_LCR);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
writel(tmp, pp->dbi_base + PCIE_RC_LCR);
if (imx6_pcie->link_gen == 2) {
/* Allow Gen2 mode after the link is up. */
tmp = readl(pp->dbi_base + PCIE_RC_LCR);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
writel(tmp, pp->dbi_base + PCIE_RC_LCR);
} else {
dev_info(pp->dev, "Link: Gen2 disabled\n");
}
/*
* Start Directed Speed Change so the best possible speed both link
@ -499,8 +504,7 @@ static int imx6_pcie_establish_link(struct pcie_port *pp)
}
tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
dev_info(pp->dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
return 0;
err_reset_phy:
@ -678,6 +682,12 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
&imx6_pcie->tx_swing_low))
imx6_pcie->tx_swing_low = 127;
/* Limit link speed */
ret = of_property_read_u32(pp->dev->of_node, "fsl,max-link-speed",
&imx6_pcie->link_gen);
if (ret)
imx6_pcie->link_gen = 1;
ret = imx6_add_pcie_port(pp, pdev);
if (ret < 0)
return ret;