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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-07 20:33:58 -04:00
Merge "dt-bindings: clock: gcc: Add PCIe pipe and UFS symbol clocks"
This commit is contained in:
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commit
a629a82df8
1 changed files with 208 additions and 192 deletions
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@ -8,200 +8,216 @@
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/* GCC HW clocks */
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#define CORE_BI_PLL_TEST_SE 0
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#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 1
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#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 2
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#define PCIE_0_PIPE_CLK 1
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#define PCIE_1_PIPE_CLK 2
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#define UFS_CARD_RX_SYMBOL_0_CLK 3
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#define UFS_CARD_RX_SYMBOL_1_CLK 4
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#define UFS_CARD_TX_SYMBOL_0_CLK 5
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#define UFS_PHY_RX_SYMBOL_0_CLK 6
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#define UFS_PHY_RX_SYMBOL_1_CLK 7
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#define UFS_PHY_TX_SYMBOL_0_CLK 8
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#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 9
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#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 10
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/* GCC clocks */
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#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 3
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#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 4
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#define GCC_AGGRE_NOC_PCIE_TBU_CLK 5
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#define GCC_AGGRE_UFS_CARD_AXI_CLK 6
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#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 7
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 8
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 9
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 10
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 11
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#define GCC_BOOT_ROM_AHB_CLK 12
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#define GCC_CAMERA_AHB_CLK 13
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#define GCC_CAMERA_HF_AXI_CLK 14
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#define GCC_CAMERA_SF_AXI_CLK 15
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#define GCC_CAMERA_XO_CLK 16
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 18
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#define GCC_CPUSS_AHB_CLK 19
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#define GCC_CPUSS_AHB_CLK_SRC 20
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 21
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#define GCC_DDRSS_GPU_AXI_CLK 22
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#define GCC_DDRSS_PCIE_SF_TBU_CLK 23
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#define GCC_DISP_AHB_CLK 24
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#define GCC_DISP_HF_AXI_CLK 25
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#define GCC_DISP_SF_AXI_CLK 26
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#define GCC_DISP_XO_CLK 27
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#define GCC_GP1_CLK 28
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#define GCC_GP1_CLK_SRC 29
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#define GCC_GP2_CLK 30
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#define GCC_GP2_CLK_SRC 31
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#define GCC_GP3_CLK 32
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#define GCC_GP3_CLK_SRC 33
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#define GCC_GPLL0 34
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#define GCC_GPLL0_OUT_EVEN 35
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#define GCC_GPLL4 36
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#define GCC_GPLL9 37
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#define GCC_GPU_CFG_AHB_CLK 38
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#define GCC_GPU_GPLL0_CLK_SRC 39
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 40
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#define GCC_GPU_IREF_EN 41
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#define GCC_GPU_MEMNOC_GFX_CLK 42
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#define GCC_GPU_SNOC_DVM_GFX_CLK 43
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#define GCC_PCIE0_PHY_RCHNG_CLK 44
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#define GCC_PCIE1_PHY_RCHNG_CLK 45
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#define GCC_PCIE_0_AUX_CLK 46
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#define GCC_PCIE_0_AUX_CLK_SRC 47
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#define GCC_PCIE_0_CFG_AHB_CLK 48
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#define GCC_PCIE_0_CLKREF_EN 49
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#define GCC_PCIE_0_MSTR_AXI_CLK 50
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51
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#define GCC_PCIE_0_PIPE_CLK 52
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#define GCC_PCIE_0_SLV_AXI_CLK 53
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 54
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#define GCC_PCIE_1_AUX_CLK 55
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#define GCC_PCIE_1_AUX_CLK_SRC 56
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#define GCC_PCIE_1_CFG_AHB_CLK 57
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#define GCC_PCIE_1_CLKREF_EN 58
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#define GCC_PCIE_1_MSTR_AXI_CLK 59
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 60
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#define GCC_PCIE_1_PIPE_CLK 61
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#define GCC_PCIE_1_SLV_AXI_CLK 62
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63
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#define GCC_PDM2_CLK 64
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#define GCC_PDM2_CLK_SRC 65
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#define GCC_PDM_AHB_CLK 66
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#define GCC_PDM_XO4_CLK 67
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 68
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 69
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#define GCC_QMIP_DISP_AHB_CLK 70
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 71
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 72
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 73
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#define GCC_QUPV3_WRAP0_CORE_CLK 74
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#define GCC_QUPV3_WRAP0_S0_CLK 75
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 76
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#define GCC_QUPV3_WRAP0_S1_CLK 77
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 78
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#define GCC_QUPV3_WRAP0_S2_CLK 79
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 80
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#define GCC_QUPV3_WRAP0_S3_CLK 81
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 82
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#define GCC_QUPV3_WRAP0_S4_CLK 83
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 84
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#define GCC_QUPV3_WRAP0_S5_CLK 85
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 86
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#define GCC_QUPV3_WRAP0_S6_CLK 87
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 88
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#define GCC_QUPV3_WRAP0_S7_CLK 89
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 90
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 91
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#define GCC_QUPV3_WRAP1_CORE_CLK 92
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#define GCC_QUPV3_WRAP1_S0_CLK 93
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 94
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#define GCC_QUPV3_WRAP1_S1_CLK 95
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 96
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#define GCC_QUPV3_WRAP1_S2_CLK 97
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 98
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#define GCC_QUPV3_WRAP1_S3_CLK 99
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 100
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#define GCC_QUPV3_WRAP1_S4_CLK 101
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 102
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#define GCC_QUPV3_WRAP1_S5_CLK 103
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 104
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#define GCC_QUPV3_WRAP2_CORE_2X_CLK 105
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#define GCC_QUPV3_WRAP2_CORE_CLK 106
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#define GCC_QUPV3_WRAP2_S0_CLK 107
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 108
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#define GCC_QUPV3_WRAP2_S1_CLK 109
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 110
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#define GCC_QUPV3_WRAP2_S2_CLK 111
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 112
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#define GCC_QUPV3_WRAP2_S3_CLK 113
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 114
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#define GCC_QUPV3_WRAP2_S4_CLK 115
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#define GCC_QUPV3_WRAP2_S4_CLK_SRC 116
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#define GCC_QUPV3_WRAP2_S5_CLK 117
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#define GCC_QUPV3_WRAP2_S5_CLK_SRC 118
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 121
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 122
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#define GCC_QUPV3_WRAP_2_M_AHB_CLK 123
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#define GCC_QUPV3_WRAP_2_S_AHB_CLK 124
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#define GCC_SDCC2_AHB_CLK 125
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#define GCC_SDCC2_APPS_CLK 126
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#define GCC_SDCC2_APPS_CLK_SRC 127
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#define GCC_SDCC4_AHB_CLK 128
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#define GCC_SDCC4_APPS_CLK 129
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#define GCC_SDCC4_APPS_CLK_SRC 130
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 131
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#define GCC_THROTTLE_PCIE_AHB_CLK 132
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#define GCC_UFS_1_CLKREF_EN 133
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#define GCC_UFS_CARD_AHB_CLK 134
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#define GCC_UFS_CARD_AXI_CLK 135
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#define GCC_UFS_CARD_AXI_CLK_SRC 136
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#define GCC_UFS_CARD_AXI_HW_CTL_CLK 137
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#define GCC_UFS_CARD_ICE_CORE_CLK 138
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#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 139
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#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 140
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#define GCC_UFS_CARD_PHY_AUX_CLK 141
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#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 142
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#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 143
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 144
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 145
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 146
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK 147
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 148
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#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 149
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#define GCC_UFS_PHY_AHB_CLK 150
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#define GCC_UFS_PHY_AXI_CLK 151
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#define GCC_UFS_PHY_AXI_CLK_SRC 152
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 153
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#define GCC_UFS_PHY_ICE_CORE_CLK 154
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 155
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156
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#define GCC_UFS_PHY_PHY_AUX_CLK 157
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 158
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 159
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 160
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 161
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 162
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 163
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 164
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 165
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#define GCC_USB30_PRIM_MASTER_CLK 166
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 167
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 168
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 169
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 170
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#define GCC_USB30_PRIM_SLEEP_CLK 171
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#define GCC_USB30_SEC_MASTER_CLK 172
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#define GCC_USB30_SEC_MASTER_CLK_SRC 173
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 174
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 175
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#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 176
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#define GCC_USB30_SEC_SLEEP_CLK 177
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#define GCC_USB3_PRIM_PHY_AUX_CLK 178
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 179
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 180
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 181
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 182
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#define GCC_USB3_SEC_CLKREF_EN 183
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#define GCC_USB3_SEC_PHY_AUX_CLK 184
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 185
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 186
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#define GCC_USB3_SEC_PHY_PIPE_CLK 187
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#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 188
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#define GCC_VIDEO_AHB_CLK 189
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#define GCC_VIDEO_AXI0_CLK 190
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#define GCC_VIDEO_AXI1_CLK 191
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#define GCC_VIDEO_XO_CLK 192
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#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 11
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#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 12
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#define GCC_AGGRE_NOC_PCIE_TBU_CLK 13
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#define GCC_AGGRE_UFS_CARD_AXI_CLK 14
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#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 15
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 16
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 17
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 18
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 19
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#define GCC_BOOT_ROM_AHB_CLK 20
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#define GCC_CAMERA_AHB_CLK 21
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#define GCC_CAMERA_HF_AXI_CLK 22
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#define GCC_CAMERA_SF_AXI_CLK 23
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#define GCC_CAMERA_XO_CLK 24
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 25
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 26
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#define GCC_CPUSS_AHB_CLK 27
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#define GCC_CPUSS_AHB_CLK_SRC 28
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 29
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#define GCC_DDRSS_GPU_AXI_CLK 30
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#define GCC_DDRSS_PCIE_SF_TBU_CLK 31
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#define GCC_DISP_AHB_CLK 32
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#define GCC_DISP_HF_AXI_CLK 33
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#define GCC_DISP_SF_AXI_CLK 34
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#define GCC_DISP_XO_CLK 35
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#define GCC_GP1_CLK 36
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#define GCC_GP1_CLK_SRC 37
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#define GCC_GP2_CLK 38
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#define GCC_GP2_CLK_SRC 39
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#define GCC_GP3_CLK 40
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#define GCC_GP3_CLK_SRC 41
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#define GCC_GPLL0 42
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#define GCC_GPLL0_OUT_EVEN 43
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#define GCC_GPLL4 44
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#define GCC_GPLL9 45
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#define GCC_GPU_CFG_AHB_CLK 46
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#define GCC_GPU_GPLL0_CLK_SRC 47
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 48
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#define GCC_GPU_IREF_EN 49
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#define GCC_GPU_MEMNOC_GFX_CLK 50
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#define GCC_GPU_SNOC_DVM_GFX_CLK 51
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#define GCC_PCIE0_PHY_RCHNG_CLK 52
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#define GCC_PCIE1_PHY_RCHNG_CLK 53
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#define GCC_PCIE_0_AUX_CLK 54
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#define GCC_PCIE_0_AUX_CLK_SRC 55
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#define GCC_PCIE_0_CFG_AHB_CLK 56
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#define GCC_PCIE_0_CLKREF_EN 57
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#define GCC_PCIE_0_MSTR_AXI_CLK 58
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 59
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#define GCC_PCIE_0_PIPE_CLK 60
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#define GCC_PCIE_0_PIPE_CLK_SRC 61
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#define GCC_PCIE_0_SLV_AXI_CLK 62
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 63
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#define GCC_PCIE_1_AUX_CLK 64
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#define GCC_PCIE_1_AUX_CLK_SRC 65
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#define GCC_PCIE_1_CFG_AHB_CLK 66
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#define GCC_PCIE_1_CLKREF_EN 67
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#define GCC_PCIE_1_MSTR_AXI_CLK 68
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 69
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#define GCC_PCIE_1_PIPE_CLK 70
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#define GCC_PCIE_1_PIPE_CLK_SRC 71
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#define GCC_PCIE_1_SLV_AXI_CLK 72
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 73
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#define GCC_PDM2_CLK 74
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#define GCC_PDM2_CLK_SRC 75
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#define GCC_PDM_AHB_CLK 76
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#define GCC_PDM_XO4_CLK 77
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 78
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 79
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#define GCC_QMIP_DISP_AHB_CLK 80
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 82
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 83
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#define GCC_QUPV3_WRAP0_CORE_CLK 84
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#define GCC_QUPV3_WRAP0_S0_CLK 85
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 86
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#define GCC_QUPV3_WRAP0_S1_CLK 87
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 88
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#define GCC_QUPV3_WRAP0_S2_CLK 89
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 90
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#define GCC_QUPV3_WRAP0_S3_CLK 91
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 92
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#define GCC_QUPV3_WRAP0_S4_CLK 93
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 94
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#define GCC_QUPV3_WRAP0_S5_CLK 95
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 96
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#define GCC_QUPV3_WRAP0_S6_CLK 97
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 98
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#define GCC_QUPV3_WRAP0_S7_CLK 99
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 100
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 101
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#define GCC_QUPV3_WRAP1_CORE_CLK 102
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#define GCC_QUPV3_WRAP1_S0_CLK 103
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 104
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#define GCC_QUPV3_WRAP1_S1_CLK 105
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 106
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#define GCC_QUPV3_WRAP1_S2_CLK 107
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 108
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#define GCC_QUPV3_WRAP1_S3_CLK 109
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 110
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#define GCC_QUPV3_WRAP1_S4_CLK 111
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 112
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#define GCC_QUPV3_WRAP1_S5_CLK 113
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 114
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#define GCC_QUPV3_WRAP2_CORE_2X_CLK 115
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#define GCC_QUPV3_WRAP2_CORE_CLK 116
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#define GCC_QUPV3_WRAP2_S0_CLK 117
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 118
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#define GCC_QUPV3_WRAP2_S1_CLK 119
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 120
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#define GCC_QUPV3_WRAP2_S2_CLK 121
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 122
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#define GCC_QUPV3_WRAP2_S3_CLK 123
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 124
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#define GCC_QUPV3_WRAP2_S4_CLK 125
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||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 126
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#define GCC_QUPV3_WRAP2_S5_CLK 127
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 128
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||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 129
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 130
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 131
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 132
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 133
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 134
|
||||
#define GCC_SDCC2_AHB_CLK 135
|
||||
#define GCC_SDCC2_APPS_CLK 136
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 137
|
||||
#define GCC_SDCC4_AHB_CLK 138
|
||||
#define GCC_SDCC4_APPS_CLK 139
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 140
|
||||
#define GCC_SYS_NOC_CPUSS_AHB_CLK 141
|
||||
#define GCC_THROTTLE_PCIE_AHB_CLK 142
|
||||
#define GCC_UFS_1_CLKREF_EN 143
|
||||
#define GCC_UFS_CARD_AHB_CLK 144
|
||||
#define GCC_UFS_CARD_AXI_CLK 145
|
||||
#define GCC_UFS_CARD_AXI_CLK_SRC 146
|
||||
#define GCC_UFS_CARD_AXI_HW_CTL_CLK 147
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK 148
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 149
|
||||
#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 150
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK 151
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 152
|
||||
#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 153
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 154
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 155
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 156
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 157
|
||||
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158
|
||||
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 159
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 160
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 161
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 162
|
||||
#define GCC_UFS_PHY_AHB_CLK 163
|
||||
#define GCC_UFS_PHY_AXI_CLK 164
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 165
|
||||
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 166
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 167
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 168
|
||||
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 169
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 170
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 171
|
||||
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 172
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 173
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 174
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 175
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 176
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 177
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 178
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 179
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 180
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 181
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 182
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 183
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 184
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 185
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 186
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 187
|
||||
#define GCC_USB30_SEC_MASTER_CLK 188
|
||||
#define GCC_USB30_SEC_MASTER_CLK_SRC 189
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK 190
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 191
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 192
|
||||
#define GCC_USB30_SEC_SLEEP_CLK 193
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 194
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 195
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 196
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 197
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 198
|
||||
#define GCC_USB3_SEC_CLKREF_EN 199
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK 200
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 201
|
||||
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 202
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK 203
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 204
|
||||
#define GCC_VIDEO_AHB_CLK 205
|
||||
#define GCC_VIDEO_AXI0_CLK 206
|
||||
#define GCC_VIDEO_AXI1_CLK 207
|
||||
#define GCC_VIDEO_XO_CLK 208
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_CAMERA_BCR 0
|
||||
|
|
|
|||
Loading…
Reference in a new issue