From a6c095841c2712cb088e5fc470f86e38f78fdf63 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 28 Dec 2020 17:49:43 +0530 Subject: [PATCH] ARM: dts: msm: add display dt node for yupik target Add display related dt nodes for yupik target. Change-Id: I6c703e83fb174c65157fb3b6604e900857abba5c --- display/yupik-sde-common.dtsi | 325 ++++++++++++++++++++++++++ display/yupik-sde-display-common.dtsi | 119 ++++++++++ display/yupik-sde-display-idp.dtsi | 22 ++ display/yupik-sde-display.dtsi | 42 ++++ display/yupik-sde.dtsi | 107 +++++++++ 5 files changed, 615 insertions(+) create mode 100644 display/yupik-sde-common.dtsi create mode 100644 display/yupik-sde-display-common.dtsi create mode 100644 display/yupik-sde-display-idp.dtsi create mode 100644 display/yupik-sde-display.dtsi create mode 100644 display/yupik-sde.dtsi diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi new file mode 100644 index 000000000000..a91404665c0a --- /dev/null +++ b/display/yupik-sde-common.dtsi @@ -0,0 +1,325 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clock-rate = <0 0 0 0 506666667 19200000 506666667 19200000>; + clock-max-rate = <0 0 0 0 608000000 19200000 608000000 + 608000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 + 0x19000 0x1a000 0x1b000>; + qcom,sde-ctl-size = <0x1e8>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", + "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", + "none", "none"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x35000 0x36000 + 0x3a000>; + qcom,sde-intf-size = <0x2c4>; + qcom,sde-intf-type = "dp", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0>; + + qcom,sde-pp-off = <0x6a000 + 0x6c000 0x6d000>; + qcom,sde-pp-slave = <0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000>; + qcom,sde-dsc-size = <0x10>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00>; + qcom,sde-dsc-ctl-size = <0x10>; + qcom,sde-dsc-native422-supp = <1>; + qcom,sde-dsc-linewidth = <2048>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", + "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 + 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 + 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0 3 2>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, + <0x2ac 8>, <0x2b4 8>, <0x2bc 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, + <0x2b0 12>, <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2400>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-wb-linewidth-linear = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x8 0x2>, + <0x7 0x1>; + qcom,sde-ubwc-version = <0x300>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <4700000>; + qcom,sde-max-bw-high-kbps = <8800000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>; + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x1 0xff00 0xff00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666666 0x66666540>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x4000901>; + + /* SPMI address related to display */ + qcom,pmic-arb = <&spmi_bus>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00040000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.5"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.1"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf01004 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi new file mode 100644 index 000000000000..a8c8e500697a --- /dev/null +++ b/display/yupik-sde-display-common.dtsi @@ -0,0 +1,119 @@ +#include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb: dsi_panel_pwr_supply_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_144_video>; + }; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 08 02 04 00 1c 18]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + +&dsi_nt36672e_fhd_plus_60_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 + 0a 09 02 04 00 1f 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi new file mode 100644 index 000000000000..31e06dd7bacc --- /dev/null +++ b/display/yupik-sde-display-idp.dtsi @@ -0,0 +1,22 @@ +#include "yupik-sde-display.dtsi" + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_144_video>; +}; + diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi new file mode 100644 index 000000000000..e85af3a1b632 --- /dev/null +++ b/display/yupik-sde-display.dtsi @@ -0,0 +1,42 @@ +#include "yupik-sde-display-common.dtsi" + +&soc { + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 80 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L12C>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; +}; + +&mdss_mdp { + connectors = <&sde_wb &sde_dsi>; +}; diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi new file mode 100644 index 000000000000..464d7c34968c --- /dev/null +++ b/display/yupik-sde.dtsi @@ -0,0 +1,107 @@ +#include "yupik-sde-common.dtsi" +#include + +&soc { + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + status = "disabled"; + reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <4>; + + qcom,sde-dram-channels = <2>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + qcom,msm-bus,active-only; + interconnects = + <&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus"; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x900 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent-hint-cached; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x901 0x400>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &cnoc2 SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010001>; + /* offsets are based off dspp 0 */ + qcom,sde-dspp-ltm-off = <0x15300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + +};