From a6da8d4052405b722e5fe0268e9d66909cfb2185 Mon Sep 17 00:00:00 2001 From: Vivek Aknurwar Date: Wed, 19 Feb 2020 18:42:26 -0800 Subject: [PATCH] ARM: dts: msm: Update all gdsc time out to 500 us Default 100 us gdsc time out may not be enough to enable gdsc as at various gdsc seqeunces and handshakes dependding on software state gdsc takes more time to get enabled. Increse does not account for configured delay, polling will exit as soon as gdsc is enabled. Change is to save unncessary debug session/efforts where gdsc gets enabled over default timeout. Change-Id: Ia9f9426ebdfd0333cded9694e6c187b7e94b6507 --- qcom/lahaina.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 9eb219fcfe9b..d87de26f8786 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -912,6 +912,7 @@ compatible = "qcom,gdsc"; reg = <0xad07004 0x4>; regulator-name = "cam_cc_bps_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -924,6 +925,7 @@ compatible = "qcom,gdsc"; reg = <0xad0a004 0x4>; regulator-name = "cam_cc_ife_0_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -935,6 +937,7 @@ compatible = "qcom,gdsc"; reg = <0xad0b004 0x4>; regulator-name = "cam_cc_ife_1_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -946,6 +949,7 @@ compatible = "qcom,gdsc"; reg = <0xad0b070 0x4>; regulator-name = "cam_cc_ife_2_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -957,6 +961,7 @@ compatible = "qcom,gdsc"; reg = <0xad08004 0x4>; regulator-name = "cam_cc_ipe_0_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -969,6 +974,7 @@ compatible = "qcom,gdsc"; reg = <0xad09004 0x4>; regulator-name = "cam_cc_sbi_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -980,6 +986,7 @@ compatible = "qcom,gdsc"; reg = <0xad0c120 0x4>; regulator-name = "cam_cc_titan_top_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -992,6 +999,7 @@ compatible = "qcom,gdsc"; reg = <0xaf03000 0x4>; regulator-name = "disp_cc_mdss_core_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -1007,6 +1015,7 @@ compatible = "qcom,gdsc"; reg = <0x16b004 0x4>; regulator-name = "gcc_pcie_0_gdsc"; + qcom,gds-timeout = <500>; parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; }; @@ -1015,6 +1024,7 @@ compatible = "qcom,gdsc"; reg = <0x18d004 0x4>; regulator-name = "gcc_pcie_1_gdsc"; + qcom,gds-timeout = <500>; parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; }; @@ -1023,6 +1033,7 @@ compatible = "qcom,gdsc"; reg = <0x175004 0x4>; regulator-name = "gcc_ufs_card_gdsc"; + qcom,gds-timeout = <500>; parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; }; @@ -1031,6 +1042,7 @@ compatible = "qcom,gdsc"; reg = <0x177004 0x4>; regulator-name = "gcc_ufs_phy_gdsc"; + qcom,gds-timeout = <500>; parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; }; @@ -1039,6 +1051,7 @@ compatible = "qcom,gdsc"; reg = <0x10f004 0x4>; regulator-name = "gcc_usb30_prim_gdsc"; + qcom,gds-timeout = <500>; parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; }; @@ -1047,6 +1060,7 @@ compatible = "qcom,gdsc"; reg = <0x110004 0x4>; regulator-name = "gcc_usb30_sec_gdsc"; + qcom,gds-timeout = <500>; parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; }; @@ -1115,6 +1129,7 @@ compatible = "qcom,gdsc"; reg = <0x3d9100c 0x4>; regulator-name = "gpu_cc_gx_gdsc"; + qcom,gds-timeout = <500>; domain-addr = <&gpu_cc_gx_domain_addr>; sw-reset = <&gpu_cc_gx_sw_reset>; parent-supply = <&VDD_GFX_LEVEL>; @@ -1128,6 +1143,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0d18 0x4>; regulator-name = "video_cc_mvs0_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -1140,6 +1156,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0bf8 0x4>; regulator-name = "video_cc_mvs0c_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -1151,6 +1168,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0d98 0x4>; regulator-name = "video_cc_mvs1_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; @@ -1163,6 +1181,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0c98 0x4>; regulator-name = "video_cc_mvs1c_gdsc"; + qcom,gds-timeout = <500>; clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>;