From a72f365a37bf16dee04dcb865d56e5e6dd90dc53 Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Tue, 21 Jan 2020 12:49:11 -0700 Subject: [PATCH] msm: kgsl: Remove references to adreno_regs from target specific code The adreno_regs are supposed to used to do register offset lookups from generic code. Since the target specific code already knows the register offset it wants the lookup step is unessesary. Change-Id: Ic0dedbad839e75006078b6d29ee99179a6680ade Signed-off-by: Jordan Crouse --- drivers/gpu/msm/adreno_a3xx.c | 8 ++++---- drivers/gpu/msm/adreno_a3xx_snapshot.c | 8 ++++---- drivers/gpu/msm/adreno_a5xx.c | 17 ++++++++++------- drivers/gpu/msm/adreno_a5xx_preempt.c | 26 ++++++++++++++------------ drivers/gpu/msm/adreno_a6xx.c | 22 +++++++++++++--------- drivers/gpu/msm/adreno_a6xx_preempt.c | 26 ++++++++++++++------------ drivers/gpu/msm/adreno_a6xx_rgmu.c | 18 +++++++----------- 7 files changed, 66 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c index acaba5e6b8bf..103ef3855730 100644 --- a/drivers/gpu/msm/adreno_a3xx.c +++ b/drivers/gpu/msm/adreno_a3xx.c @@ -602,6 +602,7 @@ static void a3xx_microcode_load(struct adreno_device *adreno_dev); static int a3xx_rb_start(struct adreno_device *adreno_dev) { + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct adreno_ringbuffer *rb = ADRENO_CURRENT_RINGBUFFER(adreno_dev); /* @@ -611,17 +612,16 @@ static int a3xx_rb_start(struct adreno_device *adreno_dev) * in certain circumstances. */ - adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL, + kgsl_regwrite(device, A3XX_CP_RB_CNTL, (ilog2(KGSL_RB_DWORDS >> 1) & 0x3F) | (1 << 27)); - adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_BASE, - rb->buffer_desc->gpuaddr); + kgsl_regwrite(device, A3XX_CP_RB_BASE, rb->buffer_desc->gpuaddr); a3xx_microcode_load(adreno_dev); /* clear ME_HALT to start micro engine */ - adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, 0); + kgsl_regwrite(device, A3XX_CP_ME_CNTL, 0); return a3xx_send_me_init(adreno_dev, rb); } diff --git a/drivers/gpu/msm/adreno_a3xx_snapshot.c b/drivers/gpu/msm/adreno_a3xx_snapshot.c index 2d582d6bdf2d..204800bfc269 100644 --- a/drivers/gpu/msm/adreno_a3xx_snapshot.c +++ b/drivers/gpu/msm/adreno_a3xx_snapshot.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2017,2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2017,2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -353,7 +353,7 @@ void a3xx_snapshot(struct adreno_device *adreno_dev, unsigned int reg, val; /* Disable Clock gating temporarily for the debug bus to work */ - adreno_writereg(adreno_dev, ADRENO_REG_RBBM_CLOCK_CTL, 0x00); + kgsl_regwrite(device, A3XX_RBBM_CLOCK_CTL, 0x0); SNAPSHOT_REGISTERS(device, snapshot, a3xx_registers); @@ -393,9 +393,9 @@ void a3xx_snapshot(struct adreno_device *adreno_dev, * care about the contents of the CP anymore. */ - adreno_readreg(adreno_dev, ADRENO_REG_CP_ME_CNTL, ®); + kgsl_regread(device, A3XX_CP_ME_CNTL, ®); reg |= (1 << 27) | (1 << 28); - adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, reg); + kgsl_regwrite(device, A3XX_CP_ME_CNTL, reg); kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, a3xx_snapshot_cp_pfp_ram, NULL); diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c index 44df04d017fb..5f3d40da7fe1 100644 --- a/drivers/gpu/msm/adreno_a5xx.c +++ b/drivers/gpu/msm/adreno_a5xx.c @@ -1814,14 +1814,14 @@ static int a5xx_send_me_init(struct adreno_device *adreno_dev, static int a5xx_rb_start(struct adreno_device *adreno_dev) { struct adreno_ringbuffer *rb = ADRENO_CURRENT_RINGBUFFER(adreno_dev); - struct kgsl_device *device = &adreno_dev->dev; + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); uint64_t addr; int ret; addr = SCRATCH_RPTR_GPU_ADDR(device, rb->id); - adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_RPTR_ADDR_LO, - ADRENO_REG_CP_RB_RPTR_ADDR_HI, addr); + kgsl_regwrite(device, A5XX_CP_RB_RPTR_ADDR_LO, lower_32_bits(addr)); + kgsl_regwrite(device, A5XX_CP_RB_RPTR_ADDR_HI, upper_32_bits(addr)); /* * The size of the ringbuffer in the hardware is the log2 @@ -1830,18 +1830,21 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev) * in certain circumstances. */ - adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL, + kgsl_regwrite(device, A5XX_CP_RB_CNTL, A5XX_CP_RB_CNTL_DEFAULT); - adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE, - ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc->gpuaddr); + kgsl_regwrite(device, A5XX_CP_RB_BASE, + lower_32_bits(rb->buffer_desc->gpuaddr)); + kgsl_regwrite(device, A5XX_CP_RB_BASE_HI, + upper_32_bits(rb->buffer_desc->gpuaddr)); ret = a5xx_microcode_load(adreno_dev); if (ret) return ret; /* clear ME_HALT to start micro engine */ - adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, 0); + + kgsl_regwrite(device, A5XX_CP_ME_CNTL, 0); ret = a5xx_send_me_init(adreno_dev, rb); if (ret) diff --git a/drivers/gpu/msm/adreno_a5xx_preempt.c b/drivers/gpu/msm/adreno_a5xx_preempt.c index c6fce546534b..4e89832f8e11 100644 --- a/drivers/gpu/msm/adreno_a5xx_preempt.c +++ b/drivers/gpu/msm/adreno_a5xx_preempt.c @@ -16,17 +16,17 @@ static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) { + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct adreno_ringbuffer *rb = adreno_dev->cur_rb; unsigned int wptr; unsigned long flags; spin_lock_irqsave(&rb->preempt_lock, flags); - adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_WPTR, &wptr); + kgsl_regread(device, A5XX_CP_RB_WPTR, &wptr); if (wptr != rb->wptr) { - adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_WPTR, - rb->wptr); + kgsl_regwrite(device, A5XX_CP_RB_WPTR, rb->wptr); /* * In case something got submitted while preemption was on * going, reset the timer. @@ -54,7 +54,7 @@ static void _a5xx_preemption_done(struct adreno_device *adreno_dev) if (!kgsl_state_is_awake(device)) return; - adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &status); + kgsl_regread(device, A5XX_CP_CONTEXT_SWITCH_CNTL, &status); if (status != 0) { dev_err(device->dev, @@ -103,7 +103,7 @@ static void _a5xx_preemption_fault(struct adreno_device *adreno_dev) * was successful then just transition to the complete state */ if (kgsl_state_is_awake(device)) { - adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &status); + kgsl_regread(device, A5XX_CP_CONTEXT_SWITCH_CNTL, &status); if (status == 0) { adreno_set_preempt_state(adreno_dev, @@ -253,18 +253,19 @@ void a5xx_preemption_trigger(struct adreno_device *adreno_dev) adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_TRIGGERED); /* Trigger the preemption */ - adreno_writereg(adreno_dev, ADRENO_REG_CP_PREEMPT, 1); + kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_CNTL, 1); } void a5xx_preempt_callback(struct adreno_device *adreno_dev, int bit) { + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); unsigned int status; if (!adreno_move_preempt_state(adreno_dev, ADRENO_PREEMPT_TRIGGERED, ADRENO_PREEMPT_PENDING)) return; - adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &status); + kgsl_regread(device, A5XX_CP_CONTEXT_SWITCH_CNTL, &status); if (status != 0) { dev_err(KGSL_DEVICE(adreno_dev)->dev, @@ -278,7 +279,7 @@ void a5xx_preempt_callback(struct adreno_device *adreno_dev, int bit) * there then we have to assume something bad happened */ adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_COMPLETE); - adreno_dispatcher_schedule(KGSL_DEVICE(adreno_dev)); + adreno_dispatcher_schedule(device); return; } @@ -454,10 +455,11 @@ void a5xx_preemption_start(struct adreno_device *adreno_dev) PREEMPT_SMMU_RECORD(context_idr), MMU_DEFAULT_CONTEXTIDR(device)); - adreno_writereg64(adreno_dev, - ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO, - ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI, - iommu->smmu_info->gpuaddr); + kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO, + lower_32_bits(iommu->smmu_info->gpuaddr)); + + kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI, + upper_32_bits(iommu->smmu_info->gpuaddr)); FOR_EACH_RINGBUFFER(adreno_dev, rb, i) { /* diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 90589b127661..ce733705a7f0 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -856,7 +856,7 @@ static int a6xx_post_start(struct adreno_device *adreno_dev) static int a6xx_rb_start(struct adreno_device *adreno_dev) { struct adreno_ringbuffer *rb = ADRENO_CURRENT_RINGBUFFER(adreno_dev); - struct kgsl_device *device = &adreno_dev->dev; + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); uint64_t addr; int ret; @@ -864,18 +864,21 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev) addr = SCRATCH_RPTR_GPU_ADDR(device, rb->id); - adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_RPTR_ADDR_LO, - ADRENO_REG_CP_RB_RPTR_ADDR_HI, addr); + kgsl_regwrite(device, A6XX_CP_RB_RPTR_ADDR_LO, lower_32_bits(addr)); + kgsl_regwrite(device, A6XX_CP_RB_RPTR_ADDR_HI, upper_32_bits(addr)); /* * The size of the ringbuffer in the hardware is the log2 * representation of the size in quadwords (sizedwords / 2). */ - adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL, + kgsl_regwrite(device, A6XX_CP_RB_CNTL, A6XX_CP_RB_CNTL_DEFAULT); - adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE, - ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc->gpuaddr); + kgsl_regwrite(device, A6XX_CP_RB_BASE, + lower_32_bits(rb->buffer_desc->gpuaddr)); + + kgsl_regwrite(device, A6XX_CP_RB_BASE_HI, + upper_32_bits(rb->buffer_desc->gpuaddr)); ret = a6xx_microcode_load(adreno_dev); if (ret) @@ -975,11 +978,12 @@ unsigned int a6xx_set_marker( static void a6xx_gpu_keepalive(struct adreno_device *adreno_dev, bool state) { - if (!gmu_core_isenabled(KGSL_DEVICE(adreno_dev))) + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); + + if (!gmu_core_isenabled(device)) return; - adreno_write_gmureg(adreno_dev, - ADRENO_REG_GMU_PWR_COL_KEEPALIVE, state); + gmu_core_regwrite(device, A6XX_GMU_GMU_PWR_COL_KEEPALIVE, state); } static bool a6xx_hw_isidle(struct adreno_device *adreno_dev) diff --git a/drivers/gpu/msm/adreno_a6xx_preempt.c b/drivers/gpu/msm/adreno_a6xx_preempt.c index 827b551d4f02..48090907f443 100644 --- a/drivers/gpu/msm/adreno_a6xx_preempt.c +++ b/drivers/gpu/msm/adreno_a6xx_preempt.c @@ -24,6 +24,7 @@ enum { static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) { + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct adreno_ringbuffer *rb = adreno_dev->cur_rb; unsigned long flags; int ret = 0; @@ -47,10 +48,9 @@ static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) } else { unsigned int wptr; - adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_WPTR, &wptr); + kgsl_regread(device, A6XX_CP_RB_WPTR, &wptr); if (wptr != rb->wptr) { - adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_WPTR, - rb->wptr); + kgsl_regwrite(device, A6XX_CP_RB_WPTR, rb->wptr); reset_timer = true; } } @@ -83,7 +83,7 @@ static void _a6xx_preemption_done(struct adreno_device *adreno_dev) if (!kgsl_state_is_awake(device)) return; - adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &status); + kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, &status); if (status & 0x1) { dev_err(device->dev, @@ -106,7 +106,7 @@ static void _a6xx_preemption_done(struct adreno_device *adreno_dev) del_timer_sync(&adreno_dev->preempt.timer); - adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT_LEVEL_STATUS, &status); + kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_LEVEL_STATUS, &status); trace_adreno_preempt_done(adreno_dev->cur_rb, adreno_dev->next_rb, status); @@ -137,7 +137,7 @@ static void _a6xx_preemption_fault(struct adreno_device *adreno_dev) * was successful then just transition to the complete state */ if (kgsl_state_is_awake(device)) { - adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &status); + kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, &status); if (status == 0) { adreno_set_preempt_state(adreno_dev, @@ -386,13 +386,14 @@ err: void a6xx_preemption_callback(struct adreno_device *adreno_dev, int bit) { + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); unsigned int status; if (!adreno_move_preempt_state(adreno_dev, ADRENO_PREEMPT_TRIGGERED, ADRENO_PREEMPT_PENDING)) return; - adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &status); + kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, &status); if (status & 0x1) { dev_err(KGSL_DEVICE(adreno_dev)->dev, @@ -422,7 +423,7 @@ void a6xx_preemption_callback(struct adreno_device *adreno_dev, int bit) del_timer(&adreno_dev->preempt.timer); - adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT_LEVEL_STATUS, &status); + kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_LEVEL_STATUS, &status); trace_adreno_preempt_done(adreno_dev->cur_rb, adreno_dev->next_rb, status); @@ -571,10 +572,11 @@ void a6xx_preemption_start(struct adreno_device *adreno_dev) PREEMPT_SMMU_RECORD(context_idr), MMU_DEFAULT_CONTEXTIDR(device)); - adreno_writereg64(adreno_dev, - ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO, - ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI, - iommu->smmu_info->gpuaddr); + kgsl_regwrite(device, A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO, + lower_32_bits(iommu->smmu_info->gpuaddr)); + + kgsl_regwrite(device, A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI, + upper_32_bits(iommu->smmu_info->gpuaddr)); FOR_EACH_RINGBUFFER(adreno_dev, rb, i) { /* diff --git a/drivers/gpu/msm/adreno_a6xx_rgmu.c b/drivers/gpu/msm/adreno_a6xx_rgmu.c index 719c19a63b9b..1cac86b8623a 100644 --- a/drivers/gpu/msm/adreno_a6xx_rgmu.c +++ b/drivers/gpu/msm/adreno_a6xx_rgmu.c @@ -35,19 +35,17 @@ irqreturn_t rgmu_irq_handler(int irq, void *data) { struct kgsl_device *device = data; struct rgmu_device *rgmu = KGSL_RGMU_DEVICE(device); - struct adreno_device *adreno_dev = ADRENO_DEVICE(device); unsigned int status = 0; - adreno_read_gmureg(adreno_dev, - ADRENO_REG_GMU_AO_HOST_INTERRUPT_STATUS, &status); + gmu_core_regread(device, A6XX_GMU_AO_HOST_INTERRUPT_STATUS, &status); if (status & RGMU_AO_IRQ_FENCE_ERR) { unsigned int fence_status; - adreno_read_gmureg(adreno_dev, - ADRENO_REG_GMU_AHB_FENCE_STATUS, &fence_status); - adreno_write_gmureg(adreno_dev, - ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR, status); + gmu_core_regread(device, A6XX_GMU_AHB_FENCE_STATUS, + &fence_status); + gmu_core_regwrite(device, A6XX_GMU_AO_HOST_INTERRUPT_CLR, + status); dev_err_ratelimited(&rgmu->pdev->dev, "FENCE error interrupt received %x\n", fence_status); @@ -68,12 +66,10 @@ irqreturn_t oob_irq_handler(int irq, void *data) struct adreno_device *adreno_dev = ADRENO_DEVICE(device); unsigned int status = 0; - adreno_read_gmureg(adreno_dev, - ADRENO_REG_GMU_GMU2HOST_INTR_INFO, &status); + gmu_core_regread(device, A6XX_GMU_GMU2HOST_INTR_INFO, &status); if (status & RGMU_OOB_IRQ_ERR_MSG) { - adreno_write_gmureg(adreno_dev, - ADRENO_REG_GMU_GMU2HOST_INTR_CLR, status); + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR, status); dev_err_ratelimited(&rgmu->pdev->dev, "RGMU oob irq error\n");