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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add SMMU devices for SM6150
Add the device tree nodes that describe the APPS and graphics SMMU for SM6150. Change-Id: I1e8af4c7297294165a60d9acdf6ac450d5b0fd3f
This commit is contained in:
Yadu MG
Shreyas K K
parent
1a65fb0285
commit
a7360253cf
2 changed files with 251 additions and 0 deletions
249
qcom/msm-arm-smmu-sm6150.dtsi
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249
qcom/msm-arm-smmu-sm6150.dtsi
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@ -0,0 +1,249 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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kgsl_smmu: kgsl-smmu@0x50a0000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x50a0000 0x10000>,
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<0x50c2000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,dynamic;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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qcom,disable-atos;
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#global-interrupts = <1>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gpu_cx_gdsc>;
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clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
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clock-names = "gcc_gpu_memnoc_gfx_clk",
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"gcc_gpu_snoc_dvm_gfx_clk",
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"gpu_cc_ahb_clk",
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"gpu_cc_hlos1_vote_gpu_smmu_clk";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
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gfx_0_tbu: gfx_0_tbu@0x50c5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x50c5000 0x1000>,
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<0x50c2200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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};
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gfx_1_tbu: gfx_1_tbu@0x50c9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x50c9000 0x1000>,
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<0x50c2208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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};
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};
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apps_smmu: apps-smmu@0x15000000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x15000000 0x80000>,
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<0x150c2000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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qcom,disable-atos;
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,active-only;
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anoc_1_tbu: anoc_1_tbu@0x150c5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150c5000 0x1000>,
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<0x150c2200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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};
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anoc_2_tbu: anoc_2_tbu@0x150c9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150c9000 0x1000>,
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<0x150c2208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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};
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mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150cd000 0x1000>,
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<0x150c2210 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
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qcom,active-only;
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interconnects = <&mmss_noc MASTER_MDP0
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&mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
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};
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mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150d1000 0x1000>,
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<0x150c2218 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0xc00 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
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qcom,active-only;
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interconnects = <&mmss_noc MASTER_CAMNOC_SF
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&mmss_noc SLAVE_MNOC_SF_MEM_NOC>;
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};
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compute_dsp_tbu: compute_dsp_tbu@0x150d5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150d5000 0x1000>,
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<0x150c2220 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1000 0x400>;
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/* No GDSC */
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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};
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adsp_tbu: adsp_tbu@0x150d9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150d9000 0x1000>,
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<0x150c2228 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1400 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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};
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};
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kgsl_iommu_test_device {
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compatible = "iommu-debug-test";
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iommus = <&kgsl_smmu 0x7 0>;
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};
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kgsl_iommu_coherent_test_device {
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compatible = "iommu-debug-test";
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iommus = <&kgsl_smmu 0x9 0>;
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dma-coherent;
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};
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apps_iommu_test_device {
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compatible = "iommu-debug-test";
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iommus = <&apps_smmu 0x21 0>;
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};
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apps_iommu_coherent_test_device {
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compatible = "iommu-debug-test";
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iommus = <&apps_smmu 0x23 0>;
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dma-coherent;
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};
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};
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&kgsl_smmu {
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qcom,actlr =
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/* All CBs of GFX: +15 deep PF */
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<0x0 0x7ff 0x303>;
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};
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&apps_smmu {
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qcom,actlr =
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/* HF and SF TBUs: +3 deep PF */
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<0x800 0x7ff 0x103>;
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};
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@ -1663,3 +1663,5 @@
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&venus_gdsc {
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status = "ok"
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};
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#include "msm-arm-smmu-sm6150.dtsi"
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