mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 08:36:12 -04:00
Merge "iommu/arm-smmu: add qcom smmuv2 support"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
a77137ef57
4 changed files with 292 additions and 63 deletions
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@ -163,6 +163,8 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
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return cavium_smmu_impl_init(smmu);
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case QCOM_SMMUV500:
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return qsmmuv500_impl_init(smmu);
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case QCOM_SMMUV2:
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return qsmmuv2_impl_init(smmu);
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default:
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break;
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}
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@ -15,6 +15,270 @@
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#include "arm-smmu.h"
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#define ARM_SMMU_IMPL_DEF1 6
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#define IMPL_DEF1_MICRO_MMU_CTRL 0
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#define MICRO_MMU_CTRL_LOCAL_HALT_REQ BIT(2)
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#define MICRO_MMU_CTRL_IDLE BIT(3)
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/* Definitions for implementation-defined registers */
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#define ACTLR_QCOM_OSH BIT(28)
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#define ACTLR_QCOM_ISH BIT(29)
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#define ACTLR_QCOM_NSH BIT(30)
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struct arm_smmu_impl_def_reg {
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u32 offset;
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u32 value;
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};
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struct qsmmuv2_archdata {
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spinlock_t atos_lock;
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struct arm_smmu_impl_def_reg *impl_def_attach_registers;
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unsigned int num_impl_def_attach_registers;
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struct arm_smmu_device smmu;
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};
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#define to_qsmmuv2_archdata(smmu) \
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container_of(smmu, struct qsmmuv2_archdata, smmu)
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static int qsmmuv2_wait_for_halt(struct arm_smmu_device *smmu)
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{
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void __iomem *reg = arm_smmu_page(smmu, ARM_SMMU_IMPL_DEF1);
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struct device *dev = smmu->dev;
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u32 tmp;
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if (readl_poll_timeout_atomic(reg + IMPL_DEF1_MICRO_MMU_CTRL, tmp,
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(tmp & MICRO_MMU_CTRL_IDLE), 0, 30000)) {
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dev_err(dev, "Couldn't halt SMMU!\n");
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return -EBUSY;
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}
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return 0;
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}
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static int __qsmmuv2_halt(struct arm_smmu_device *smmu, bool wait)
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{
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u32 val;
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val = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF1,
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IMPL_DEF1_MICRO_MMU_CTRL);
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val |= MICRO_MMU_CTRL_LOCAL_HALT_REQ;
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arm_smmu_writel(smmu, ARM_SMMU_IMPL_DEF1, IMPL_DEF1_MICRO_MMU_CTRL,
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val);
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return wait ? qsmmuv2_wait_for_halt(smmu) : 0;
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}
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static int qsmmuv2_halt(struct arm_smmu_device *smmu)
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{
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return __qsmmuv2_halt(smmu, true);
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}
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static int qsmmuv2_halt_nowait(struct arm_smmu_device *smmu)
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{
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return __qsmmuv2_halt(smmu, false);
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}
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static void qsmmuv2_resume(struct arm_smmu_device *smmu)
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{
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u32 val;
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val = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF1,
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IMPL_DEF1_MICRO_MMU_CTRL);
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val &= ~MICRO_MMU_CTRL_LOCAL_HALT_REQ;
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arm_smmu_writel(smmu, ARM_SMMU_IMPL_DEF1, IMPL_DEF1_MICRO_MMU_CTRL,
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val);
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}
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static phys_addr_t __qsmmuv2_iova_to_phys_hard(
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struct arm_smmu_domain *smmu_domain,
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dma_addr_t iova)
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{
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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struct device *dev = smmu->dev;
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int idx = cfg->cbndx;
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void __iomem *reg;
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u32 tmp;
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u64 phys;
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unsigned long va;
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/* ATS1 registers can only be written atomically */
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va = iova & ~0xfffUL;
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
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arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_ATS1PR, va);
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else
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va);
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reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx));
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if (readl_poll_timeout_atomic(reg + ARM_SMMU_CB_ATSR, tmp,
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!(tmp & ATSR_ACTIVE), 5, 50)) {
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dev_err(dev, "iova to phys timed out on %pad.\n", &iova);
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phys = 0;
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return phys;
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}
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phys = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_PAR);
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if (phys & CB_PAR_F) {
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dev_err(dev, "translation fault!\n");
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dev_err(dev, "PAR = 0x%llx\n", phys);
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phys = 0;
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} else {
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phys = (phys & (PHYS_MASK & ~0xfffULL)) | (iova & 0xfff);
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}
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return phys;
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}
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static phys_addr_t qsmmuv2_iova_to_phys_hard(
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struct arm_smmu_domain *smmu_domain,
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dma_addr_t iova,
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unsigned long trans_flags)
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{
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct qsmmuv2_archdata *data = to_qsmmuv2_archdata(smmu);
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int idx = smmu_domain->cfg.cbndx;
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phys_addr_t phys = 0;
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unsigned long flags;
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u32 sctlr, sctlr_orig, fsr;
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spin_lock_irqsave(&data->atos_lock, flags);
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qsmmuv2_halt_nowait(smmu);
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/* disable stall mode momentarily */
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sctlr_orig = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_SCTLR);
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sctlr = sctlr_orig & ~(SCTLR_CFCFG);
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr);
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/* clear FSR to allow ATOS to log any faults */
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fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
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if (fsr & FSR_FAULT) {
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/* Clear pending interrupts */
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
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/*
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* Barrier required to ensure that the FSR is cleared
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* before resuming SMMU operation.
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*/
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wmb();
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/*
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* TBU halt takes care of resuming any stalled transcation.
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* Kept it here for completeness sake.
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*/
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if (fsr & FSR_SS)
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
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RESUME_TERMINATE);
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}
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qsmmuv2_wait_for_halt(smmu);
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phys = __qsmmuv2_iova_to_phys_hard(smmu_domain, iova);
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/* restore SCTLR */
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr_orig);
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qsmmuv2_resume(smmu);
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spin_unlock_irqrestore(&data->atos_lock, flags);
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return phys;
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}
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static int qsmmuv2_device_reset(struct arm_smmu_device *smmu)
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{
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struct qsmmuv2_archdata *data = to_qsmmuv2_archdata(smmu);
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struct arm_smmu_impl_def_reg *regs = data->impl_def_attach_registers;
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u32 i;
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/* Program implementation defined registers */
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qsmmuv2_halt(smmu);
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for (i = 0; i < data->num_impl_def_attach_registers; ++i)
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arm_smmu_gr0_write(smmu, regs[i].offset, regs[i].value);
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qsmmuv2_resume(smmu);
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return 0;
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}
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static void qsmmuv2_init_cb(struct arm_smmu_domain *smmu_domain,
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struct device *dev)
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{
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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int idx = smmu_domain->cfg.cbndx;
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const struct iommu_flush_ops *tlb;
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u32 val;
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tlb = smmu_domain->pgtbl_info[0].pgtbl_cfg.tlb;
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val = ACTLR_QCOM_ISH | ACTLR_QCOM_OSH | ACTLR_QCOM_NSH;
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ACTLR, val);
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/*
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* Flush the context bank after modifying ACTLR to ensure there
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* are no cache entries with stale state
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*/
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tlb->tlb_flush_all(smmu_domain);
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}
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static int arm_smmu_parse_impl_def_registers(struct arm_smmu_device *smmu)
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{
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struct device *dev = smmu->dev;
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struct qsmmuv2_archdata *data = to_qsmmuv2_archdata(smmu);
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int i, ntuples, ret;
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u32 *tuples;
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struct arm_smmu_impl_def_reg *regs, *regit;
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if (!of_find_property(dev->of_node, "attach-impl-defs", &ntuples))
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return 0;
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ntuples /= sizeof(u32);
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if (ntuples % 2) {
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dev_err(dev,
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"Invalid number of attach-impl-defs registers: %d\n",
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ntuples);
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return -EINVAL;
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}
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regs = devm_kzalloc(dev, sizeof(*data->impl_def_attach_registers) *
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ntuples, GFP_KERNEL);
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if (!regs)
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return -ENOMEM;
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tuples = kzalloc(sizeof(u32) * ntuples * 2, GFP_KERNEL);
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if (!tuples)
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return -ENOMEM;
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ret = of_property_read_u32_array(dev->of_node, "attach-impl-defs",
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tuples, ntuples);
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if (ret) {
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kfree(tuples);
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return ret;
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}
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for (i = 0, regit = regs; i < ntuples; i += 2, ++regit) {
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regit->offset = tuples[i];
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regit->value = tuples[i + 1];
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}
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kfree(tuples);
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data->impl_def_attach_registers = regs;
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data->num_impl_def_attach_registers = ntuples / 2;
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return 0;
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}
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static const struct arm_smmu_impl qsmmuv2_impl = {
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.init_context_bank = qsmmuv2_init_cb,
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.iova_to_phys_hard = qsmmuv2_iova_to_phys_hard,
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.reset = qsmmuv2_device_reset,
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};
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struct qcom_smmu {
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struct arm_smmu_device smmu;
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};
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@ -927,3 +1191,28 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
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return &qsmmu->smmu;
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}
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struct arm_smmu_device *qsmmuv2_impl_init(struct arm_smmu_device *smmu)
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{
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struct device *dev = smmu->dev;
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struct qsmmuv2_archdata *data;
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struct platform_device *pdev;
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int ret;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return ERR_PTR(-ENOMEM);
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pdev = to_platform_device(dev);
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spin_lock_init(&data->atos_lock);
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data->smmu = *smmu;
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data->smmu.impl = &qsmmuv2_impl;
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ret = arm_smmu_parse_impl_def_registers(&data->smmu);
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if (ret)
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return ERR_PTR(ret);
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devm_kfree(smmu->dev, smmu);
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return &data->smmu;
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}
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@ -68,9 +68,6 @@
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#define TLB_LOOP_TIMEOUT 500000 /* 500ms */
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#define TLB_LOOP_INC_MAX 1000 /*1ms*/
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#define ARM_SMMU_IMPL_DEF1(smmu) \
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((smmu)->base + (6 * (1 << (smmu)->pgshift)))
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#define MSI_IOVA_BASE 0x8000000
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#define MSI_IOVA_LENGTH 0x100000
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@ -4264,53 +4261,6 @@ static int arm_smmu_handoff_cbs(struct arm_smmu_device *smmu)
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return 0;
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}
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static int arm_smmu_parse_impl_def_registers(struct arm_smmu_device *smmu)
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{
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struct device *dev = smmu->dev;
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int i, ntuples, ret;
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u32 *tuples;
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struct arm_smmu_impl_def_reg *regs, *regit;
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if (!of_find_property(dev->of_node, "attach-impl-defs", &ntuples))
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return 0;
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ntuples /= sizeof(u32);
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if (ntuples % 2) {
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dev_err(dev,
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"Invalid number of attach-impl-defs registers: %d\n",
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ntuples);
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return -EINVAL;
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}
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regs = devm_kmalloc(
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dev, sizeof(*smmu->impl_def_attach_registers) * ntuples,
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GFP_KERNEL);
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if (!regs)
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return -ENOMEM;
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tuples = devm_kmalloc(dev, sizeof(u32) * ntuples * 2, GFP_KERNEL);
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if (!tuples)
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return -ENOMEM;
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ret = of_property_read_u32_array(dev->of_node, "attach-impl-defs",
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tuples, ntuples);
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if (ret)
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return ret;
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for (i = 0, regit = regs; i < ntuples; i += 2, ++regit) {
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regit->offset = tuples[i];
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regit->value = tuples[i + 1];
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}
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devm_kfree(dev, tuples);
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smmu->impl_def_attach_registers = regs;
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smmu->num_impl_def_attach_registers = ntuples / 2;
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return 0;
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}
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static int arm_smmu_init_clocks(struct arm_smmu_power_resources *pwr)
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{
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const char *cname;
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@ -4908,10 +4858,6 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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if (err)
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goto out_power_off;
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err = arm_smmu_parse_impl_def_registers(smmu);
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if (err)
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goto out_power_off;
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if (smmu->version == ARM_SMMU_V2) {
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if (smmu->num_context_banks > smmu->num_context_irqs) {
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dev_err(dev,
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@ -279,11 +279,6 @@ enum arm_smmu_implementation {
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QCOM_SMMUV500,
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};
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struct arm_smmu_impl_def_reg {
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u32 offset;
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u32 value;
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};
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/*
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* Describes resources required for on/off power operation.
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* Separate reference count is provided for atomic/nonatomic
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@ -400,10 +395,6 @@ struct arm_smmu_device {
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/* IOMMU core code handle */
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struct iommu_device iommu;
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/* Specific to QCOM */
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struct arm_smmu_impl_def_reg *impl_def_attach_registers;
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unsigned int num_impl_def_attach_registers;
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struct arm_smmu_power_resources *pwr;
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/* protects idr */
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@ -587,6 +578,7 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,
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struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu);
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struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
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struct arm_smmu_device *qsmmuv500_impl_init(struct arm_smmu_device *smmu);
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struct arm_smmu_device *qsmmuv2_impl_init(struct arm_smmu_device *smmu);
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int arm_mmu500_reset(struct arm_smmu_device *smmu);
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