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Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6

Browse source
This commit is contained in:
Linus Torvalds 2005-11-09 08:34:36 -08:00
commit a7c243b544
35 changed files with 8276 additions and 3801 deletions
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2
drivers/net/Kconfig
View file

@ -447,7 +447,7 @@ config NET_SB1250_MAC
config SGI_IOC3_ETH
bool "SGI IOC3 Ethernet"
depends on NET_ETHERNET && PCI && SGI_IP27 && BROKEN
depends on NET_ETHERNET && PCI && SGI_IP27
select CRC32
select MII
help

179
drivers/net/b44.c
View file

@ -28,8 +28,8 @@
#define DRV_MODULE_NAME "b44"
#define PFX DRV_MODULE_NAME ": "
#define DRV_MODULE_VERSION "0.95"
#define DRV_MODULE_RELDATE "Aug 3, 2004"
#define DRV_MODULE_VERSION "0.96"
#define DRV_MODULE_RELDATE "Nov 8, 2005"
#define B44_DEF_MSG_ENABLE \
(NETIF_MSG_DRV | \
@ -101,14 +101,16 @@ MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
static void b44_halt(struct b44 *);
static void b44_init_rings(struct b44 *);
static void b44_init_hw(struct b44 *);
static int b44_poll(struct net_device *dev, int *budget);
#ifdef CONFIG_NET_POLL_CONTROLLER
static void b44_poll_controller(struct net_device *dev);
#endif
static int dma_desc_align_mask;
static int dma_desc_sync_size;
static const char b44_gstrings[][ETH_GSTRING_LEN] = {
#define _B44(x...) # x,
B44_STAT_REG_DECLARE
#undef _B44
};
static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
dma_addr_t dma_base,
unsigned long offset,
@ -501,7 +503,10 @@ static void b44_stats_update(struct b44 *bp)
for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
*val++ += br32(bp, reg);
}
val = &bp->hw_stats.rx_good_octets;
/* Pad */
reg += 8*4UL;
for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
*val++ += br32(bp, reg);
}
@ -652,7 +657,7 @@ static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
/* Hardware bug work-around, the chip is unable to do PCI DMA
to/from anything above 1GB :-( */
if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
/* Sigh... */
pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
dev_kfree_skb_any(skb);
@ -662,7 +667,7 @@ static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
mapping = pci_map_single(bp->pdev, skb->data,
RX_PKT_BUF_SZ,
PCI_DMA_FROMDEVICE);
if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
dev_kfree_skb_any(skb);
return -ENOMEM;
@ -889,11 +894,10 @@ static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device *dev = dev_id;
struct b44 *bp = netdev_priv(dev);
unsigned long flags;
u32 istat, imask;
int handled = 0;
spin_lock_irqsave(&bp->lock, flags);
spin_lock(&bp->lock);
istat = br32(bp, B44_ISTAT);
imask = br32(bp, B44_IMASK);
@ -904,6 +908,12 @@ static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
istat &= imask;
if (istat) {
handled = 1;
if (unlikely(!netif_running(dev))) {
printk(KERN_INFO "%s: late interrupt.\n", dev->name);
goto irq_ack;
}
if (netif_rx_schedule_prep(dev)) {
/* NOTE: These writes are posted by the readback of
* the ISTAT register below.
@ -916,10 +926,11 @@ static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
dev->name);
}
irq_ack:
bw32(bp, B44_ISTAT, istat);
br32(bp, B44_ISTAT);
}
spin_unlock_irqrestore(&bp->lock, flags);
spin_unlock(&bp->lock);
return IRQ_RETVAL(handled);
}
@ -947,6 +958,7 @@ static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct b44 *bp = netdev_priv(dev);
struct sk_buff *bounce_skb;
int rc = NETDEV_TX_OK;
dma_addr_t mapping;
u32 len, entry, ctrl;
@ -956,29 +968,28 @@ static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
/* This is a hard error, log it. */
if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
netif_stop_queue(dev);
spin_unlock_irq(&bp->lock);
printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
dev->name);
return 1;
goto err_out;
}
mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
if(mapping+len > B44_DMA_MASK) {
if (mapping + len > B44_DMA_MASK) {
/* Chip can't handle DMA to/from >1GB, use bounce buffer */
pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
GFP_ATOMIC|GFP_DMA);
if (!bounce_skb)
return NETDEV_TX_BUSY;
goto err_out;
mapping = pci_map_single(bp->pdev, bounce_skb->data,
len, PCI_DMA_TODEVICE);
if(mapping+len > B44_DMA_MASK) {
if (mapping + len > B44_DMA_MASK) {
pci_unmap_single(bp->pdev, mapping,
len, PCI_DMA_TODEVICE);
dev_kfree_skb_any(bounce_skb);
return NETDEV_TX_BUSY;
goto err_out;
}
memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
@ -1018,11 +1029,16 @@ static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
if (TX_BUFFS_AVAIL(bp) < 1)
netif_stop_queue(dev);
spin_unlock_irq(&bp->lock);
dev->trans_start = jiffies;
return 0;
out_unlock:
spin_unlock_irq(&bp->lock);
return rc;
err_out:
rc = NETDEV_TX_BUSY;
goto out_unlock;
}
static int b44_change_mtu(struct net_device *dev, int new_mtu)
@ -1096,8 +1112,7 @@ static void b44_free_rings(struct b44 *bp)
*
* The chip has been shut down and the driver detached from
* the networking, so no interrupts or new tx packets will
* end up in the driver. bp->lock is not held and we are not
* in an interrupt context and thus may sleep.
* end up in the driver.
*/
static void b44_init_rings(struct b44 *bp)
{
@ -1169,16 +1184,14 @@ static int b44_alloc_consistent(struct b44 *bp)
int size;
size = B44_RX_RING_SIZE * sizeof(struct ring_info);
bp->rx_buffers = kmalloc(size, GFP_KERNEL);
bp->rx_buffers = kzalloc(size, GFP_KERNEL);
if (!bp->rx_buffers)
goto out_err;
memset(bp->rx_buffers, 0, size);
size = B44_TX_RING_SIZE * sizeof(struct ring_info);
bp->tx_buffers = kmalloc(size, GFP_KERNEL);
bp->tx_buffers = kzalloc(size, GFP_KERNEL);
if (!bp->tx_buffers)
goto out_err;
memset(bp->tx_buffers, 0, size);
size = DMA_TABLE_BYTES;
bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
@ -1189,10 +1202,10 @@ static int b44_alloc_consistent(struct b44 *bp)
struct dma_desc *rx_ring;
dma_addr_t rx_ring_dma;
if (!(rx_ring = (struct dma_desc *)kmalloc(size, GFP_KERNEL)))
rx_ring = kzalloc(size, GFP_KERNEL);
if (!rx_ring)
goto out_err;
memset(rx_ring, 0, size);
rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
DMA_TABLE_BYTES,
DMA_BIDIRECTIONAL);
@ -1215,10 +1228,10 @@ static int b44_alloc_consistent(struct b44 *bp)
struct dma_desc *tx_ring;
dma_addr_t tx_ring_dma;
if (!(tx_ring = (struct dma_desc *)kmalloc(size, GFP_KERNEL)))
tx_ring = kzalloc(size, GFP_KERNEL);
if (!tx_ring)
goto out_err;
memset(tx_ring, 0, size);
tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
DMA_TABLE_BYTES,
DMA_TO_DEVICE);
@ -1381,22 +1394,21 @@ static int b44_open(struct net_device *dev)
err = b44_alloc_consistent(bp);
if (err)
return err;
err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
if (err)
goto err_out_free;
spin_lock_irq(&bp->lock);
goto out;
b44_init_rings(bp);
b44_init_hw(bp);
bp->flags |= B44_FLAG_INIT_COMPLETE;
netif_carrier_off(dev);
b44_check_phy(bp);
spin_unlock_irq(&bp->lock);
err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
if (unlikely(err < 0)) {
b44_chip_reset(bp);
b44_free_rings(bp);
b44_free_consistent(bp);
goto out;
}
init_timer(&bp->timer);
bp->timer.expires = jiffies + HZ;
@ -1405,11 +1417,7 @@ static int b44_open(struct net_device *dev)
add_timer(&bp->timer);
b44_enable_ints(bp);
return 0;
err_out_free:
b44_free_consistent(bp);
out:
return err;
}
@ -1444,6 +1452,8 @@ static int b44_close(struct net_device *dev)
netif_stop_queue(dev);
netif_poll_disable(dev);
del_timer_sync(&bp->timer);
spin_lock_irq(&bp->lock);
@ -1453,13 +1463,14 @@ static int b44_close(struct net_device *dev)
#endif
b44_halt(bp);
b44_free_rings(bp);
bp->flags &= ~B44_FLAG_INIT_COMPLETE;
netif_carrier_off(bp->dev);
spin_unlock_irq(&bp->lock);
free_irq(dev->irq, dev);
netif_poll_enable(dev);
b44_free_consistent(bp);
return 0;
@ -1524,8 +1535,6 @@ static void __b44_set_rx_mode(struct net_device *dev)
{
struct b44 *bp = netdev_priv(dev);
u32 val;
int i=0;
unsigned char zero[6] = {0,0,0,0,0,0};
val = br32(bp, B44_RXCONFIG);
val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
@ -1533,14 +1542,17 @@ static void __b44_set_rx_mode(struct net_device *dev)
val |= RXCONFIG_PROMISC;
bw32(bp, B44_RXCONFIG, val);
} else {
unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
int i = 0;
__b44_set_mac_addr(bp);
if (dev->flags & IFF_ALLMULTI)
val |= RXCONFIG_ALLMULTI;
else
i=__b44_load_mcast(bp, dev);
i = __b44_load_mcast(bp, dev);
for(;i<64;i++) {
for (; i < 64; i++) {
__b44_cam_write(bp, zero, i);
}
bw32(bp, B44_RXCONFIG, val);
@ -1604,7 +1616,7 @@ static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct b44 *bp = netdev_priv(dev);
if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
if (!netif_running(dev))
return -EAGAIN;
cmd->supported = (SUPPORTED_Autoneg);
cmd->supported |= (SUPPORTED_100baseT_Half |
@ -1642,7 +1654,7 @@ static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct b44 *bp = netdev_priv(dev);
if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
if (!netif_running(dev))
return -EAGAIN;
/* We do not support gigabit. */
@ -1772,6 +1784,37 @@ static int b44_set_pauseparam(struct net_device *dev,
return 0;
}
static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
switch(stringset) {
case ETH_SS_STATS:
memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
break;
}
}
static int b44_get_stats_count(struct net_device *dev)
{
return ARRAY_SIZE(b44_gstrings);
}
static void b44_get_ethtool_stats(struct net_device *dev,
struct ethtool_stats *stats, u64 *data)
{
struct b44 *bp = netdev_priv(dev);
u32 *val = &bp->hw_stats.tx_good_octets;
u32 i;
spin_lock_irq(&bp->lock);
b44_stats_update(bp);
for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
*data++ = *val++;
spin_unlock_irq(&bp->lock);
}
static struct ethtool_ops b44_ethtool_ops = {
.get_drvinfo = b44_get_drvinfo,
.get_settings = b44_get_settings,
@ -1784,6 +1827,9 @@ static struct ethtool_ops b44_ethtool_ops = {
.set_pauseparam = b44_set_pauseparam,
.get_msglevel = b44_get_msglevel,
.set_msglevel = b44_set_msglevel,
.get_strings = b44_get_strings,
.get_stats_count = b44_get_stats_count,
.get_ethtool_stats = b44_get_ethtool_stats,
.get_perm_addr = ethtool_op_get_perm_addr,
};
@ -1892,9 +1938,9 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
if (err) {
printk(KERN_ERR PFX "No usable DMA configuration, "
"aborting.\n");
goto err_out_free_res;
printk(KERN_ERR PFX "No usable DMA configuration, "
"aborting.\n");
goto err_out_free_res;
}
b44reg_base = pci_resource_start(pdev, 0);
@ -1916,10 +1962,8 @@ static int __devinit b44_init_one(struct pci_dev *pdev,
bp = netdev_priv(dev);
bp->pdev = pdev;
bp->dev = dev;
if (b44_debug >= 0)
bp->msg_enable = (1 << b44_debug) - 1;
else
bp->msg_enable = B44_DEF_MSG_ENABLE;
bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
spin_lock_init(&bp->lock);
@ -2009,17 +2053,14 @@ err_out_disable_pdev:
static void __devexit b44_remove_one(struct pci_dev *pdev)
{
struct net_device *dev = pci_get_drvdata(pdev);
struct b44 *bp = netdev_priv(dev);
if (dev) {
struct b44 *bp = netdev_priv(dev);
unregister_netdev(dev);
iounmap(bp->regs);
free_netdev(dev);
pci_release_regions(pdev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
}
unregister_netdev(dev);
iounmap(bp->regs);
free_netdev(dev);
pci_release_regions(pdev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
}
static int b44_suspend(struct pci_dev *pdev, pm_message_t state)

75
drivers/net/b44.h
View file

@ -346,29 +346,63 @@ struct ring_info {
#define B44_MCAST_TABLE_SIZE 32
#define B44_STAT_REG_DECLARE \
_B44(tx_good_octets) \
_B44(tx_good_pkts) \
_B44(tx_octets) \
_B44(tx_pkts) \
_B44(tx_broadcast_pkts) \
_B44(tx_multicast_pkts) \
_B44(tx_len_64) \
_B44(tx_len_65_to_127) \
_B44(tx_len_128_to_255) \
_B44(tx_len_256_to_511) \
_B44(tx_len_512_to_1023) \
_B44(tx_len_1024_to_max) \
_B44(tx_jabber_pkts) \
_B44(tx_oversize_pkts) \
_B44(tx_fragment_pkts) \
_B44(tx_underruns) \
_B44(tx_total_cols) \
_B44(tx_single_cols) \
_B44(tx_multiple_cols) \
_B44(tx_excessive_cols) \
_B44(tx_late_cols) \
_B44(tx_defered) \
_B44(tx_carrier_lost) \
_B44(tx_pause_pkts) \
_B44(rx_good_octets) \
_B44(rx_good_pkts) \
_B44(rx_octets) \
_B44(rx_pkts) \
_B44(rx_broadcast_pkts) \
_B44(rx_multicast_pkts) \
_B44(rx_len_64) \
_B44(rx_len_65_to_127) \
_B44(rx_len_128_to_255) \
_B44(rx_len_256_to_511) \
_B44(rx_len_512_to_1023) \
_B44(rx_len_1024_to_max) \
_B44(rx_jabber_pkts) \
_B44(rx_oversize_pkts) \
_B44(rx_fragment_pkts) \
_B44(rx_missed_pkts) \
_B44(rx_crc_align_errs) \
_B44(rx_undersize) \
_B44(rx_crc_errs) \
_B44(rx_align_errs) \
_B44(rx_symbol_errs) \
_B44(rx_pause_pkts) \
_B44(rx_nonpause_pkts)
/* SW copy of device statistics, kept up to date by periodic timer
* which probes HW values. Must have same relative layout as HW
* register above, because b44_stats_update depends upon this.
* which probes HW values. Check b44_stats_update if you mess with
* the layout
*/
struct b44_hw_stats {
u32 tx_good_octets, tx_good_pkts, tx_octets;
u32 tx_pkts, tx_broadcast_pkts, tx_multicast_pkts;
u32 tx_len_64, tx_len_65_to_127, tx_len_128_to_255;
u32 tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max;
u32 tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts;
u32 tx_underruns, tx_total_cols, tx_single_cols;
u32 tx_multiple_cols, tx_excessive_cols, tx_late_cols;
u32 tx_defered, tx_carrier_lost, tx_pause_pkts;
u32 __pad1[8];
u32 rx_good_octets, rx_good_pkts, rx_octets;
u32 rx_pkts, rx_broadcast_pkts, rx_multicast_pkts;
u32 rx_len_64, rx_len_65_to_127, rx_len_128_to_255;
u32 rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max;
u32 rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts;
u32 rx_missed_pkts, rx_crc_align_errs, rx_undersize;
u32 rx_crc_errs, rx_align_errs, rx_symbol_errs;
u32 rx_pause_pkts, rx_nonpause_pkts;
#define _B44(x) u32 x;
B44_STAT_REG_DECLARE
#undef _B44
};
struct b44 {
@ -386,7 +420,6 @@ struct b44 {
u32 dma_offset;
u32 flags;
#define B44_FLAG_INIT_COMPLETE 0x00000001
#define B44_FLAG_BUGGY_TXPTR 0x00000002
#define B44_FLAG_REORDER_BUG 0x00000004
#define B44_FLAG_PAUSE_AUTO 0x00008000

32
drivers/net/bonding/bond_main.c
View file

@ -1604,35 +1604,27 @@ static int bond_sethwaddr(struct net_device *bond_dev, struct net_device *slave_
(NETIF_F_SG|NETIF_F_IP_CSUM|NETIF_F_NO_CSUM|NETIF_F_HW_CSUM)
/*
* Compute the features available to the bonding device by
* intersection of all of the slave devices' BOND_INTERSECT_FEATURES.
* Call this after attaching or detaching a slave to update the
* bond's features.
* Compute the common dev->feature set available to all slaves. Some
* feature bits are managed elsewhere, so preserve feature bits set on
* master device that are not part of the examined set.
*/
static int bond_compute_features(struct bonding *bond)
{
int i;
unsigned long features = BOND_INTERSECT_FEATURES;
struct slave *slave;
struct net_device *bond_dev = bond->dev;
int features = bond->bond_features;
int i;
bond_for_each_slave(bond, slave, i) {
struct net_device * slave_dev = slave->dev;
if (i == 0) {
features |= BOND_INTERSECT_FEATURES;
}
features &=
~(~slave_dev->features & BOND_INTERSECT_FEATURES);
}
bond_for_each_slave(bond, slave, i)
features &= (slave->dev->features & BOND_INTERSECT_FEATURES);
/* turn off NETIF_F_SG if we need a csum and h/w can't do it */
if ((features & NETIF_F_SG) &&
!(features & (NETIF_F_IP_CSUM |
NETIF_F_NO_CSUM |
NETIF_F_HW_CSUM))) {
!(features & (NETIF_F_IP_CSUM |
NETIF_F_NO_CSUM |
NETIF_F_HW_CSUM)))
features &= ~NETIF_F_SG;
}
features |= (bond_dev->features & ~BOND_INTERSECT_FEATURES);
bond_dev->features = features;
return 0;
@ -4561,8 +4553,6 @@ static int __init bond_init(struct net_device *bond_dev, struct bond_params *par
NETIF_F_HW_VLAN_RX |
NETIF_F_HW_VLAN_FILTER);
bond->bond_features = bond_dev->features;
#ifdef CONFIG_PROC_FS
bond_create_proc_entry(bond);
#endif

7
drivers/net/bonding/bonding.h
View file

@ -40,8 +40,8 @@
#include "bond_3ad.h"
#include "bond_alb.h"
#define DRV_VERSION "2.6.4"
#define DRV_RELDATE "September 26, 2005"
#define DRV_VERSION "2.6.5"
#define DRV_RELDATE "November 4, 2005"
#define DRV_NAME "bonding"
#define DRV_DESCRIPTION "Ethernet Channel Bonding Driver"
@ -211,9 +211,6 @@ struct bonding {
struct bond_params params;
struct list_head vlan_list;
struct vlan_group *vlgrp;
/* the features the bonding device supports, independently
* of any slaves */
int bond_features;
};
/**

149
drivers/net/cris/eth_v10.c
View file

@ -409,7 +409,6 @@ static irqreturn_t e100nw_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static void e100_rx(struct net_device *dev);
static int e100_close(struct net_device *dev);
static int e100_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
static int e100_ethtool_ioctl(struct net_device* dev, struct ifreq *ifr);
static int e100_set_config(struct net_device* dev, struct ifmap* map);
static void e100_tx_timeout(struct net_device *dev);
static struct net_device_stats *e100_get_stats(struct net_device *dev);
@ -436,6 +435,8 @@ static void e100_reset_transceiver(struct net_device* net);
static void e100_clear_network_leds(unsigned long dummy);
static void e100_set_network_leds(int active);
static struct ethtool_ops e100_ethtool_ops;
static void broadcom_check_speed(struct net_device* dev);
static void broadcom_check_duplex(struct net_device* dev);
static void tdk_check_speed(struct net_device* dev);
@ -495,6 +496,7 @@ etrax_ethernet_init(void)
dev->get_stats = e100_get_stats;
dev->set_multicast_list = set_multicast_list;
dev->set_mac_address = e100_set_mac_address;
dev->ethtool_ops = &e100_ethtool_ops;
dev->do_ioctl = e100_ioctl;
dev->set_config = e100_set_config;
dev->tx_timeout = e100_tx_timeout;
@ -1448,8 +1450,6 @@ e100_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
spin_lock(&np->lock); /* Preempt protection */
switch (cmd) {
case SIOCETHTOOL:
return e100_ethtool_ioctl(dev,ifr);
case SIOCGMIIPHY: /* Get PHY address */
data->phy_id = mdio_phy_addr;
break;
@ -1486,88 +1486,81 @@ e100_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
return 0;
}
static int
e100_ethtool_ioctl(struct net_device *dev, struct ifreq *ifr)
static int e100_set_settings(struct net_device *dev,
struct ethtool_cmd *ecmd)
{
struct ethtool_cmd ecmd;
if (copy_from_user(&ecmd, ifr->ifr_data, sizeof (ecmd)))
return -EFAULT;
switch (ecmd.cmd) {
case ETHTOOL_GSET:
{
memset((void *) &ecmd, 0, sizeof (ecmd));
ecmd.supported =
SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII |
ecmd->supported = SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII |
SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
ecmd.port = PORT_TP;
ecmd.transceiver = XCVR_EXTERNAL;
ecmd.phy_address = mdio_phy_addr;
ecmd.speed = current_speed;
ecmd.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
ecmd.advertising = ADVERTISED_TP;
if (current_duplex == autoneg && current_speed_selection == 0)
ecmd.advertising |= ADVERTISED_Autoneg;
else {
ecmd.advertising |=
ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
if (current_speed_selection == 10)
ecmd.advertising &= ~(ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full);
else if (current_speed_selection == 100)
ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full);
if (current_duplex == half)
ecmd.advertising &= ~(ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Full);
else if (current_duplex == full)
ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_100baseT_Half);
}
ecmd.autoneg = AUTONEG_ENABLE;
if (copy_to_user(ifr->ifr_data, &ecmd, sizeof (ecmd)))
return -EFAULT;
}
break;
case ETHTOOL_SSET:
{
if (!capable(CAP_NET_ADMIN)) {
return -EPERM;
}
if (ecmd.autoneg == AUTONEG_ENABLE) {
e100_set_duplex(dev, autoneg);
e100_set_speed(dev, 0);
} else {
e100_set_duplex(dev, ecmd.duplex == DUPLEX_HALF ? half : full);
e100_set_speed(dev, ecmd.speed == SPEED_10 ? 10: 100);
}
}
break;
case ETHTOOL_GDRVINFO:
{
struct ethtool_drvinfo info;
memset((void *) &info, 0, sizeof (info));
strncpy(info.driver, "ETRAX 100LX", sizeof(info.driver) - 1);
strncpy(info.version, "$Revision: 1.31 $", sizeof(info.version) - 1);
strncpy(info.fw_version, "N/A", sizeof(info.fw_version) - 1);
strncpy(info.bus_info, "N/A", sizeof(info.bus_info) - 1);
info.regdump_len = 0;
info.eedump_len = 0;
info.testinfo_len = 0;
if (copy_to_user(ifr->ifr_data, &info, sizeof (info)))
return -EFAULT;
}
break;
case ETHTOOL_NWAY_RST:
if (current_duplex == autoneg && current_speed_selection == 0)
e100_negotiate(dev);
break;
default:
return -EOPNOTSUPP;
break;
ecmd->port = PORT_TP;
ecmd->transceiver = XCVR_EXTERNAL;
ecmd->phy_address = mdio_phy_addr;
ecmd->speed = current_speed;
ecmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
ecmd->advertising = ADVERTISED_TP;
if (current_duplex == autoneg && current_speed_selection == 0)
ecmd->advertising |= ADVERTISED_Autoneg;
else {
ecmd->advertising |=
ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
if (current_speed_selection == 10)
ecmd->advertising &= ~(ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full);
else if (current_speed_selection == 100)
ecmd->advertising &= ~(ADVERTISED_10baseT_Half |
ADVERTISED_10baseT_Full);
if (current_duplex == half)
ecmd->advertising &= ~(ADVERTISED_10baseT_Full |
ADVERTISED_100baseT_Full);
else if (current_duplex == full)
ecmd->advertising &= ~(ADVERTISED_10baseT_Half |
ADVERTISED_100baseT_Half);
}
ecmd->autoneg = AUTONEG_ENABLE;
return 0;
}
static int e100_set_settings(struct net_device *dev,
struct ethtool_cmd *ecmd)
{
if (ecmd->autoneg == AUTONEG_ENABLE) {
e100_set_duplex(dev, autoneg);
e100_set_speed(dev, 0);
} else {
e100_set_duplex(dev, ecmd->duplex == DUPLEX_HALF ? half : full);
e100_set_speed(dev, ecmd->speed == SPEED_10 ? 10: 100);
}
return 0;
}
static void e100_get_drvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
strncpy(info->driver, "ETRAX 100LX", sizeof(info->driver) - 1);
strncpy(info->version, "$Revision: 1.31 $", sizeof(info->version) - 1);
strncpy(info->fw_version, "N/A", sizeof(info->fw_version) - 1);
strncpy(info->bus_info, "N/A", sizeof(info->bus_info) - 1);
}
static int e100_nway_reset(struct net_device *dev)
{
if (current_duplex == autoneg && current_speed_selection == 0)
e100_negotiate(dev);
return 0;
}
static struct ethtool_ops e100_ethtool_ops = {
.get_settings = e100_get_settings,
.set_settings = e100_set_settings,
.get_drvinfo = e100_get_drvinfo,
.nway_reset = e100_nway_reset,
.get_link = ethtool_op_get_link,
};
static int
e100_set_config(struct net_device *dev, struct ifmap *map)
{

16
drivers/net/dgrs.c
View file

@ -1549,7 +1549,7 @@ MODULE_PARM_DESC(nicmode, "Digi RightSwitch operating mode (1: switch, 2: multi-
static int __init dgrs_init_module (void)
{
int i;
int eisacount = 0, pcicount = 0;
int cardcount = 0;
/*
* Command line variable overrides
@ -1591,15 +1591,13 @@ static int __init dgrs_init_module (void)
* Find and configure all the cards
*/
#ifdef CONFIG_EISA
eisacount = eisa_driver_register(&dgrs_eisa_driver);
if (eisacount < 0)
return eisacount;
#endif
#ifdef CONFIG_PCI
pcicount = pci_register_driver(&dgrs_pci_driver);
if (pcicount)
return pcicount;
cardcount = eisa_driver_register(&dgrs_eisa_driver);
if (cardcount < 0)
return cardcount;
#endif
cardcount = pci_register_driver(&dgrs_pci_driver);
if (cardcount)
return cardcount;
return 0;
}

6
drivers/net/e100.c
View file

@ -1478,7 +1478,7 @@ static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
if(pci_dma_mapping_error(rx->dma_addr)) {
dev_kfree_skb_any(rx->skb);
rx->skb = 0;
rx->skb = NULL;
rx->dma_addr = 0;
return -ENOMEM;
}
@ -1764,7 +1764,7 @@ static int e100_up(struct nic *nic)
if((err = e100_hw_init(nic)))
goto err_clean_cbs;
e100_set_multicast_list(nic->netdev);
e100_start_receiver(nic, 0);
e100_start_receiver(nic, NULL);
mod_timer(&nic->watchdog, jiffies);
if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
nic->netdev->name, nic->netdev)))
@ -1844,7 +1844,7 @@ static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
BMCR_LOOPBACK);
e100_start_receiver(nic, 0);
e100_start_receiver(nic, NULL);
if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
err = -ENOMEM;

13
drivers/net/ns83820.c
View file

@ -110,7 +110,6 @@
#include <linux/init.h>
#include <linux/ip.h> /* for iph */
#include <linux/in.h> /* for IPPROTO_... */
#include <linux/eeprom.h>
#include <linux/compiler.h>
#include <linux/prefetch.h>
#include <linux/ethtool.h>
@ -445,7 +444,6 @@ struct ns83820 {
u32 MEAR_cache;
u32 IMR_cache;
struct eeprom ee;
unsigned linkstate;
@ -1558,15 +1556,13 @@ static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
unsigned i;
for (i=0; i<3; i++) {
u32 data;
#if 0 /* I've left this in as an example of how to use eeprom.h */
data = eeprom_readw(&dev->ee, 0xa + 2 - i);
#else
/* Read from the perfect match memory: this is loaded by
* the chip from the EEPROM via the EELOAD self test.
*/
writel(i*2, dev->base + RFCR);
data = readl(dev->base + RFDR);
#endif
*mac++ = data;
*mac++ = data >> 8;
}
@ -1851,8 +1847,6 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
spin_lock_init(&dev->misc_lock);
dev->pci_dev = pci_dev;
dev->ee.cache = &dev->MEAR_cache;
dev->ee.lock = &dev->misc_lock;
SET_MODULE_OWNER(ndev);
SET_NETDEV_DEV(ndev, &pci_dev->dev);
@ -1887,9 +1881,6 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
dev->IMR_cache = 0;
setup_ee_mem_bitbanger(&dev->ee, dev->base + MEAR, 3, 2, 1, 0,
0);
err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ,
DRV_NAME, ndev);
if (err) {

43
drivers/net/s2io.c
View file

@ -1531,7 +1531,7 @@ static int init_nic(struct s2io_nic *nic)
#define LINK_UP_DOWN_INTERRUPT 1
#define MAC_RMAC_ERR_TIMER 2
int s2io_link_fault_indication(nic_t *nic)
static int s2io_link_fault_indication(nic_t *nic)
{
if (nic->intr_type != INTA)
return MAC_RMAC_ERR_TIMER;
@ -1863,7 +1863,7 @@ static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
*
*/
void fix_mac_address(nic_t * sp)
static void fix_mac_address(nic_t * sp)
{
XENA_dev_config_t __iomem *bar0 = sp->bar0;
u64 val64;
@ -2159,7 +2159,7 @@ int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
* SUCCESS on success or an appropriate -ve value on failure.
*/
int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
{
struct net_device *dev = nic->dev;
struct sk_buff *skb;
@ -2830,7 +2830,7 @@ static void alarm_intr_handler(struct s2io_nic *nic)
* SUCCESS on success and FAILURE on failure.
*/
int wait_for_cmd_complete(nic_t * sp)
static int wait_for_cmd_complete(nic_t * sp)
{
XENA_dev_config_t __iomem *bar0 = sp->bar0;
int ret = FAILURE, cnt = 0;
@ -3076,7 +3076,7 @@ int s2io_set_swapper(nic_t * sp)
return SUCCESS;
}
int wait_for_msix_trans(nic_t *nic, int i)
static int wait_for_msix_trans(nic_t *nic, int i)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
u64 val64;
@ -3115,7 +3115,7 @@ void restore_xmsi_data(nic_t *nic)
}
}
void store_xmsi_data(nic_t *nic)
static void store_xmsi_data(nic_t *nic)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
u64 val64, addr, data;
@ -3287,7 +3287,7 @@ int s2io_enable_msi_x(nic_t *nic)
* file on failure.
*/
int s2io_open(struct net_device *dev)
static int s2io_open(struct net_device *dev)
{
nic_t *sp = dev->priv;
int err = 0;
@ -3417,7 +3417,7 @@ hw_init_failed:
* file on failure.
*/
int s2io_close(struct net_device *dev)
static int s2io_close(struct net_device *dev)
{
nic_t *sp = dev->priv;
int i;
@ -3466,7 +3466,7 @@ int s2io_close(struct net_device *dev)
* 0 on success & 1 on failure.
*/
int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
{
nic_t *sp = dev->priv;
u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
@ -3912,7 +3912,7 @@ static void s2io_updt_stats(nic_t *sp)
* pointer to the updated net_device_stats structure.
*/
struct net_device_stats *s2io_get_stats(struct net_device *dev)
static struct net_device_stats *s2io_get_stats(struct net_device *dev)
{
nic_t *sp = dev->priv;
mac_info_t *mac_control;
@ -5105,19 +5105,20 @@ static void s2io_get_ethtool_stats(struct net_device *dev,
tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
}
int s2io_ethtool_get_regs_len(struct net_device *dev)
static int s2io_ethtool_get_regs_len(struct net_device *dev)
{
return (XENA_REG_SPACE);
}
u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
{
nic_t *sp = dev->priv;
return (sp->rx_csum);
}
int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
{
nic_t *sp = dev->priv;
@ -5128,17 +5129,19 @@ int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
return 0;
}
int s2io_get_eeprom_len(struct net_device *dev)
static int s2io_get_eeprom_len(struct net_device *dev)
{
return (XENA_EEPROM_SPACE);
}
int s2io_ethtool_self_test_count(struct net_device *dev)
static int s2io_ethtool_self_test_count(struct net_device *dev)
{
return (S2IO_TEST_LEN);
}
void s2io_ethtool_get_strings(struct net_device *dev,
u32 stringset, u8 * data)
static void s2io_ethtool_get_strings(struct net_device *dev,
u32 stringset, u8 * data)
{
switch (stringset) {
case ETH_SS_TEST:
@ -5154,7 +5157,7 @@ static int s2io_ethtool_get_stats_count(struct net_device *dev)
return (S2IO_STAT_LEN);
}
int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
{
if (data)
dev->features |= NETIF_F_IP_CSUM;
@ -5207,7 +5210,7 @@ static struct ethtool_ops netdev_ethtool_ops = {
* function always return EOPNOTSUPPORTED
*/
int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
return -EOPNOTSUPP;
}
@ -5223,7 +5226,7 @@ int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
* file on failure.
*/
int s2io_change_mtu(struct net_device *dev, int new_mtu)
static int s2io_change_mtu(struct net_device *dev, int new_mtu)
{
nic_t *sp = dev->priv;

267
drivers/net/skge.c
View file

@ -37,12 +37,13 @@
#include <linux/delay.h>
#include <linux/crc32.h>
#include <linux/dma-mapping.h>
#include <linux/mii.h>
#include <asm/irq.h>
#include "skge.h"
#define DRV_NAME "skge"
#define DRV_VERSION "1.1"
#define DRV_VERSION "1.2"
#define PFX DRV_NAME " "
#define DEFAULT_TX_RING_SIZE 128
@ -88,8 +89,8 @@ MODULE_DEVICE_TABLE(pci, skge_id_table);
static int skge_up(struct net_device *dev);
static int skge_down(struct net_device *dev);
static void skge_tx_clean(struct skge_port *skge);
static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
static void genesis_get_stats(struct skge_port *skge, u64 *data);
static void yukon_get_stats(struct skge_port *skge, u64 *data);
static void yukon_init(struct skge_hw *hw, int port);
@ -129,7 +130,7 @@ static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
regs->len - B3_RI_WTO_R1);
}
/* Wake on Lan only supported on Yukon chps with rev 1 or above */
/* Wake on Lan only supported on Yukon chips with rev 1 or above */
static int wol_supported(const struct skge_hw *hw)
{
return !((hw->chip_id == CHIP_ID_GENESIS ||
@ -169,8 +170,8 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
return 0;
}
/* Determine supported/adverised modes based on hardware.
* Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
/* Determine supported/advertised modes based on hardware.
* Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
*/
static u32 skge_supported_modes(const struct skge_hw *hw)
{
@ -531,13 +532,13 @@ static inline u32 hwkhz(const struct skge_hw *hw)
return 78215; /* or: 78.125 MHz */
}
/* Chip hz to microseconds */
/* Chip HZ to microseconds */
static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
{
return (ticks * 1000) / hwkhz(hw);
}
/* Microseconds to chip hz */
/* Microseconds to chip HZ */
static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
{
return hwkhz(hw) * usec / 1000;
@ -883,32 +884,37 @@ static void skge_link_down(struct skge_port *skge)
printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
}
static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
{
int i;
u16 v;
xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
v = xm_read16(hw, port, XM_PHY_DATA);
xm_read16(hw, port, XM_PHY_DATA);
/* Need to wait for external PHY */
for (i = 0; i < PHY_RETRIES; i++) {
udelay(1);
if (xm_read16(hw, port, XM_MMU_CMD)
& XM_MMU_PHY_RDY)
if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
goto ready;
}
printk(KERN_WARNING PFX "%s: phy read timed out\n",
hw->dev[port]->name);
return 0;
return -ETIMEDOUT;
ready:
v = xm_read16(hw, port, XM_PHY_DATA);
*val = xm_read16(hw, port, XM_PHY_DATA);
return 0;
}
static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
{
u16 v = 0;
if (__xm_phy_read(hw, port, reg, &v))
printk(KERN_WARNING PFX "%s: phy read timed out\n",
hw->dev[port]->name);
return v;
}
static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
{
int i;
@ -918,19 +924,11 @@ static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
goto ready;
udelay(1);
}
printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
hw->dev[port]->name);
return -EIO;
ready:
xm_write16(hw, port, XM_PHY_DATA, val);
for (i = 0; i < PHY_RETRIES; i++) {
udelay(1);
if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
return;
}
printk(KERN_WARNING PFX "%s: phy write timed out\n",
hw->dev[port]->name);
return 0;
}
static void genesis_init(struct skge_hw *hw)
@ -1165,7 +1163,7 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo)
xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
/* Use link status change interrrupt */
/* Use link status change interrupt */
xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
bcom_check_link(hw, port);
@ -1205,7 +1203,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
skge_write32(hw, B2_GP_IO, r);
skge_read32(hw, B2_GP_IO);
/* Enable GMII interfac */
/* Enable GMII interface */
xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
bcom_phy_init(skge, jumbo);
@ -1256,7 +1254,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
* that jumbo frames larger than 8192 bytes will be
* truncated. Disabling all bad frame filtering causes
* the RX FIFO to operate in streaming mode, in which
* case the XMAC will start transfering frames out of the
* case the XMAC will start transferring frames out of the
* RX FIFO as soon as the FIFO threshold is reached.
*/
xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
@ -1323,7 +1321,7 @@ static void genesis_stop(struct skge_port *skge)
port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
/*
* If the transfer stucks at the MAC the STOP command will not
* If the transfer sticks at the MAC the STOP command will not
* terminate if we don't flush the XMAC's transmit FIFO !
*/
xm_write32(hw, port, XM_MODE,
@ -1400,42 +1398,6 @@ static void genesis_mac_intr(struct skge_hw *hw, int port)
}
}
static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
{
int i;
gma_write16(hw, port, GM_SMI_DATA, val);
gma_write16(hw, port, GM_SMI_CTRL,
GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
for (i = 0; i < PHY_RETRIES; i++) {
udelay(1);
if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
break;
}
}
static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
{
int i;
gma_write16(hw, port, GM_SMI_CTRL,
GM_SMI_CT_PHY_AD(hw->phy_addr)
| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
for (i = 0; i < PHY_RETRIES; i++) {
udelay(1);
if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
goto ready;
}
printk(KERN_WARNING PFX "%s: phy read timeout\n",
hw->dev[port]->name);
return 0;
ready:
return gma_read16(hw, port, GM_SMI_DATA);
}
static void genesis_link_up(struct skge_port *skge)
{
struct skge_hw *hw = skge->hw;
@ -1549,7 +1511,55 @@ static inline void bcom_phy_intr(struct skge_port *skge)
}
/* Marvell Phy Initailization */
static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
{
int i;
gma_write16(hw, port, GM_SMI_DATA, val);
gma_write16(hw, port, GM_SMI_CTRL,
GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
for (i = 0; i < PHY_RETRIES; i++) {
udelay(1);
if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
return 0;
}
printk(KERN_WARNING PFX "%s: phy write timeout\n",
hw->dev[port]->name);
return -EIO;
}
static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
{
int i;
gma_write16(hw, port, GM_SMI_CTRL,
GM_SMI_CT_PHY_AD(hw->phy_addr)
| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
for (i = 0; i < PHY_RETRIES; i++) {
udelay(1);
if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
goto ready;
}
return -ETIMEDOUT;
ready:
*val = gma_read16(hw, port, GM_SMI_DATA);
return 0;
}
static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
{
u16 v = 0;
if (__gm_phy_read(hw, port, reg, &v))
printk(KERN_WARNING PFX "%s: phy read timeout\n",
hw->dev[port]->name);
return v;
}
/* Marvell Phy Initialization */
static void yukon_init(struct skge_hw *hw, int port)
{
struct skge_port *skge = netdev_priv(hw->dev[port]);
@ -1794,6 +1804,25 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
}
/* Go into power down mode */
static void yukon_suspend(struct skge_hw *hw, int port)
{
u16 ctrl;
ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
ctrl |= PHY_M_PC_POL_R_DIS;
gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
ctrl |= PHY_CT_RESET;
gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
/* switch IEEE compatible power down mode on */
ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
ctrl |= PHY_CT_PDOWN;
gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
}
static void yukon_stop(struct skge_port *skge)
{
struct skge_hw *hw = skge->hw;
@ -1807,14 +1836,7 @@ static void yukon_stop(struct skge_port *skge)
& ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
gma_read16(hw, port, GM_GP_CTRL);
if (hw->chip_id == CHIP_ID_YUKON_LITE &&
hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
u32 io = skge_read32(hw, B2_GP_IO);
io |= GP_DIR_9 | GP_IO_9;
skge_write32(hw, B2_GP_IO, io);
skge_read32(hw, B2_GP_IO);
}
yukon_suspend(hw, port);
/* set GPHY Control reset */
skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
@ -1997,6 +2019,51 @@ static void yukon_phy_intr(struct skge_port *skge)
/* XXX restart autonegotiation? */
}
/* Basic MII support */
static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
struct mii_ioctl_data *data = if_mii(ifr);
struct skge_port *skge = netdev_priv(dev);
struct skge_hw *hw = skge->hw;
int err = -EOPNOTSUPP;
if (!netif_running(dev))
return -ENODEV; /* Phy still in reset */
switch(cmd) {
case SIOCGMIIPHY:
data->phy_id = hw->phy_addr;
/* fallthru */
case SIOCGMIIREG: {
u16 val = 0;
spin_lock_bh(&hw->phy_lock);
if (hw->chip_id == CHIP_ID_GENESIS)
err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
else
err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
spin_unlock_bh(&hw->phy_lock);
data->val_out = val;
break;
}
case SIOCSMIIREG:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
spin_lock_bh(&hw->phy_lock);
if (hw->chip_id == CHIP_ID_GENESIS)
err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
data->val_in);
else
err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
data->val_in);
spin_unlock_bh(&hw->phy_lock);
break;
}
return err;
}
static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
{
u32 end;
@ -2089,7 +2156,7 @@ static int skge_up(struct net_device *dev)
hw->intr_mask |= portirqmask[port];
skge_write32(hw, B0_IMSK, hw->intr_mask);
/* Initialze MAC */
/* Initialize MAC */
spin_lock_bh(&hw->phy_lock);
if (hw->chip_id == CHIP_ID_GENESIS)
genesis_mac_init(hw, port);
@ -2409,7 +2476,7 @@ static void yukon_set_multicast(struct net_device *dev)
reg = gma_read16(hw, port, GM_RX_CTRL);
reg |= GM_RXCR_UCF_ENA;
if (dev->flags & IFF_PROMISC) /* promiscious */
if (dev->flags & IFF_PROMISC) /* promiscuous */
reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
else if (dev->flags & IFF_ALLMULTI) /* all multicast */
memset(filter, 0xff, sizeof(filter));
@ -2560,7 +2627,7 @@ static int skge_poll(struct net_device *dev, int *budget)
unsigned int to_do = min(dev->quota, *budget);
unsigned int work_done = 0;
for (e = ring->to_clean; work_done < to_do; e = e->next) {
for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
struct skge_rx_desc *rd = e->desc;
struct sk_buff *skb;
u32 control;
@ -2593,11 +2660,11 @@ static int skge_poll(struct net_device *dev, int *budget)
if (work_done >= to_do)
return 1; /* not done */
local_irq_disable();
__netif_rx_complete(dev);
netif_rx_complete(dev);
hw->intr_mask |= portirqmask[skge->port];
skge_write32(hw, B0_IMSK, hw->intr_mask);
local_irq_enable();
skge_read32(hw, B0_IMSK);
return 0;
}
@ -2609,7 +2676,7 @@ static inline void skge_tx_intr(struct net_device *dev)
struct skge_element *e;
spin_lock(&skge->tx_lock);
for (e = ring->to_clean; e != ring->to_use; e = e->next) {
for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
struct skge_tx_desc *td = e->desc;
u32 control;
@ -2732,7 +2799,7 @@ static void skge_error_irq(struct skge_hw *hw)
}
/*
* Interrrupt from PHY are handled in tasklet (soft irq)
* Interrupt from PHY are handled in tasklet (soft irq)
* because accessing phy registers requires spin wait which might
* cause excess interrupt latency.
*/
@ -2762,6 +2829,14 @@ static void skge_extirq(unsigned long data)
local_irq_enable();
}
static inline void skge_wakeup(struct net_device *dev)
{
struct skge_port *skge = netdev_priv(dev);
prefetch(skge->rx_ring.to_clean);
netif_rx_schedule(dev);
}
static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
{
struct skge_hw *hw = dev_id;
@ -2773,12 +2848,12 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
status &= hw->intr_mask;
if (status & IS_R1_F) {
hw->intr_mask &= ~IS_R1_F;
netif_rx_schedule(hw->dev[0]);
skge_wakeup(hw->dev[0]);
}
if (status & IS_R2_F) {
hw->intr_mask &= ~IS_R2_F;
netif_rx_schedule(hw->dev[1]);
skge_wakeup(hw->dev[1]);
}
if (status & IS_XA1_F)
@ -2893,6 +2968,7 @@ static const char *skge_board_name(const struct skge_hw *hw)
*/
static int skge_reset(struct skge_hw *hw)
{
u32 reg;
u16 ctst;
u8 t8, mac_cfg, pmd_type, phy_type;
int i;
@ -2971,6 +3047,7 @@ static int skge_reset(struct skge_hw *hw)
/* switch power to VCC (WA for VAUX problem) */
skge_write8(hw, B0_POWER_CTRL,
PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
/* avoid boards with stuck Hardware error bits */
if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
(skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
@ -2978,6 +3055,14 @@ static int skge_reset(struct skge_hw *hw)
hw->intr_mask &= ~IS_HW_ERR;
}
/* Clear PHY COMA */
skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
reg &= ~PCI_PHY_COMA;
pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
for (i = 0; i < hw->ports; i++) {
skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
@ -3048,6 +3133,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
SET_NETDEV_DEV(dev, &hw->pdev->dev);
dev->open = skge_up;
dev->stop = skge_down;
dev->do_ioctl = skge_ioctl;
dev->hard_start_xmit = skge_xmit_frame;
dev->get_stats = skge_get_stats;
if (hw->chip_id == CHIP_ID_GENESIS)
@ -3147,7 +3233,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
}
#ifdef __BIG_ENDIAN
/* byte swap decriptors in hardware */
/* byte swap descriptors in hardware */
{
u32 reg;
@ -3158,14 +3244,13 @@ static int __devinit skge_probe(struct pci_dev *pdev,
#endif
err = -ENOMEM;
hw = kmalloc(sizeof(*hw), GFP_KERNEL);
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
if (!hw) {
printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
pci_name(pdev));
goto err_out_free_regions;
}
memset(hw, 0, sizeof(*hw));
hw->pdev = pdev;
spin_lock_init(&hw->phy_lock);
tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
@ -3188,7 +3273,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
if (err)
goto err_out_free_irq;
printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
pci_resource_start(pdev, 0), pdev->irq,
skge_board_name(hw), hw->chip_rev);

2
drivers/net/skge.h
View file

@ -6,6 +6,8 @@
/* PCI config registers */
#define PCI_DEV_REG1 0x40
#define PCI_PHY_COMA 0x8000000
#define PCI_VIO 0x2000000
#define PCI_DEV_REG2 0x44
#define PCI_REV_DESC 0x4

36
drivers/net/wireless/airo.c
View file

@ -4535,9 +4535,8 @@ static int proc_status_open( struct inode *inode, struct file *file ) {
StatusRid status_rid;
int i;
if ((file->private_data = kmalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
if ((file->private_data = kzalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
return -ENOMEM;
memset(file->private_data, 0, sizeof(struct proc_data));
data = (struct proc_data *)file->private_data;
if ((data->rbuffer = kmalloc( 2048, GFP_KERNEL )) == NULL) {
kfree (file->private_data);
@ -4615,9 +4614,8 @@ static int proc_stats_rid_open( struct inode *inode,
int i, j;
u32 *vals = stats.vals;
if ((file->private_data = kmalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
if ((file->private_data = kzalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
return -ENOMEM;
memset(file->private_data, 0, sizeof(struct proc_data));
data = (struct proc_data *)file->private_data;
if ((data->rbuffer = kmalloc( 4096, GFP_KERNEL )) == NULL) {
kfree (file->private_data);
@ -4881,20 +4879,18 @@ static int proc_config_open( struct inode *inode, struct file *file ) {
struct airo_info *ai = dev->priv;
int i;
if ((file->private_data = kmalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
if ((file->private_data = kzalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
return -ENOMEM;
memset(file->private_data, 0, sizeof(struct proc_data));
data = (struct proc_data *)file->private_data;
if ((data->rbuffer = kmalloc( 2048, GFP_KERNEL )) == NULL) {
kfree (file->private_data);
return -ENOMEM;
}
if ((data->wbuffer = kmalloc( 2048, GFP_KERNEL )) == NULL) {
if ((data->wbuffer = kzalloc( 2048, GFP_KERNEL )) == NULL) {
kfree (data->rbuffer);
kfree (file->private_data);
return -ENOMEM;
}
memset( data->wbuffer, 0, 2048 );
data->maxwritelen = 2048;
data->on_close = proc_config_on_close;
@ -5155,24 +5151,21 @@ static int proc_wepkey_open( struct inode *inode, struct file *file ) {
int j=0;
int rc;
if ((file->private_data = kmalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
if ((file->private_data = kzalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
return -ENOMEM;
memset(file->private_data, 0, sizeof(struct proc_data));
memset(&wkr, 0, sizeof(wkr));
data = (struct proc_data *)file->private_data;
if ((data->rbuffer = kmalloc( 180, GFP_KERNEL )) == NULL) {
if ((data->rbuffer = kzalloc( 180, GFP_KERNEL )) == NULL) {
kfree (file->private_data);
return -ENOMEM;
}
memset(data->rbuffer, 0, 180);
data->writelen = 0;
data->maxwritelen = 80;
if ((data->wbuffer = kmalloc( 80, GFP_KERNEL )) == NULL) {
if ((data->wbuffer = kzalloc( 80, GFP_KERNEL )) == NULL) {
kfree (data->rbuffer);
kfree (file->private_data);
return -ENOMEM;
}
memset( data->wbuffer, 0, 80 );
data->on_close = proc_wepkey_on_close;
ptr = data->rbuffer;
@ -5203,9 +5196,8 @@ static int proc_SSID_open( struct inode *inode, struct file *file ) {
char *ptr;
SsidRid SSID_rid;
if ((file->private_data = kmalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
if ((file->private_data = kzalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
return -ENOMEM;
memset(file->private_data, 0, sizeof(struct proc_data));
data = (struct proc_data *)file->private_data;
if ((data->rbuffer = kmalloc( 104, GFP_KERNEL )) == NULL) {
kfree (file->private_data);
@ -5213,12 +5205,11 @@ static int proc_SSID_open( struct inode *inode, struct file *file ) {
}
data->writelen = 0;
data->maxwritelen = 33*3;
if ((data->wbuffer = kmalloc( 33*3, GFP_KERNEL )) == NULL) {
if ((data->wbuffer = kzalloc( 33*3, GFP_KERNEL )) == NULL) {
kfree (data->rbuffer);
kfree (file->private_data);
return -ENOMEM;
}
memset( data->wbuffer, 0, 33*3 );
data->on_close = proc_SSID_on_close;
readSsidRid(ai, &SSID_rid);
@ -5247,9 +5238,8 @@ static int proc_APList_open( struct inode *inode, struct file *file ) {
char *ptr;
APListRid APList_rid;
if ((file->private_data = kmalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
if ((file->private_data = kzalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
return -ENOMEM;
memset(file->private_data, 0, sizeof(struct proc_data));
data = (struct proc_data *)file->private_data;
if ((data->rbuffer = kmalloc( 104, GFP_KERNEL )) == NULL) {
kfree (file->private_data);
@ -5257,12 +5247,11 @@ static int proc_APList_open( struct inode *inode, struct file *file ) {
}
data->writelen = 0;
data->maxwritelen = 4*6*3;
if ((data->wbuffer = kmalloc( data->maxwritelen, GFP_KERNEL )) == NULL) {
if ((data->wbuffer = kzalloc( data->maxwritelen, GFP_KERNEL )) == NULL) {
kfree (data->rbuffer);
kfree (file->private_data);
return -ENOMEM;
}
memset( data->wbuffer, 0, data->maxwritelen );
data->on_close = proc_APList_on_close;
readAPListRid(ai, &APList_rid);
@ -5297,9 +5286,8 @@ static int proc_BSSList_open( struct inode *inode, struct file *file ) {
/* If doLoseSync is not 1, we won't do a Lose Sync */
int doLoseSync = -1;
if ((file->private_data = kmalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
if ((file->private_data = kzalloc(sizeof(struct proc_data ), GFP_KERNEL)) == NULL)
return -ENOMEM;
memset(file->private_data, 0, sizeof(struct proc_data));
data = (struct proc_data *)file->private_data;
if ((data->rbuffer = kmalloc( 1024, GFP_KERNEL )) == NULL) {
kfree (file->private_data);

6
drivers/net/wireless/airo_cs.c
View file

@ -170,12 +170,11 @@ static dev_link_t *airo_attach(void)
DEBUG(0, "airo_attach()\n");
/* Initialize the dev_link_t structure */
link = kmalloc(sizeof(struct dev_link_t), GFP_KERNEL);
link = kzalloc(sizeof(struct dev_link_t), GFP_KERNEL);
if (!link) {
printk(KERN_ERR "airo_cs: no memory for new device\n");
return NULL;
}
memset(link, 0, sizeof(struct dev_link_t));
/* Interrupt setup */
link->irq.Attributes = IRQ_TYPE_EXCLUSIVE;
@ -194,13 +193,12 @@ static dev_link_t *airo_attach(void)
link->conf.IntType = INT_MEMORY_AND_IO;
/* Allocate space for private device-specific data */
local = kmalloc(sizeof(local_info_t), GFP_KERNEL);
local = kzalloc(sizeof(local_info_t), GFP_KERNEL);
if (!local) {
printk(KERN_ERR "airo_cs: no memory for new device\n");
kfree (link);
return NULL;
}
memset(local, 0, sizeof(local_info_t));
link->priv = local;
/* Register with Card Services */

2
drivers/net/wireless/atmel.c
View file

@ -2217,7 +2217,7 @@ static int atmel_get_range(struct net_device *dev,
int k,i,j;
dwrq->length = sizeof(struct iw_range);
memset(range, 0, sizeof(range));
memset(range, 0, sizeof(struct iw_range));
range->min_nwid = 0x0000;
range->max_nwid = 0x0000;
range->num_channels = 0;

6
drivers/net/wireless/atmel_cs.c
View file

@ -180,12 +180,11 @@ static dev_link_t *atmel_attach(void)
DEBUG(0, "atmel_attach()\n");
/* Initialize the dev_link_t structure */
link = kmalloc(sizeof(struct dev_link_t), GFP_KERNEL);
link = kzalloc(sizeof(struct dev_link_t), GFP_KERNEL);
if (!link) {
printk(KERN_ERR "atmel_cs: no memory for new device\n");
return NULL;
}
memset(link, 0, sizeof(struct dev_link_t));
/* Interrupt setup */
link->irq.Attributes = IRQ_TYPE_EXCLUSIVE;
@ -204,13 +203,12 @@ static dev_link_t *atmel_attach(void)
link->conf.IntType = INT_MEMORY_AND_IO;
/* Allocate space for private device-specific data */
local = kmalloc(sizeof(local_info_t), GFP_KERNEL);
local = kzalloc(sizeof(local_info_t), GFP_KERNEL);
if (!local) {
printk(KERN_ERR "atmel_cs: no memory for new device\n");
kfree (link);
return NULL;
}
memset(local, 0, sizeof(local_info_t));
link->priv = local;
/* Register with Card Services */

2868
drivers/net/wireless/ipw2100.c
View file

File diff suppressed because it is too large Load diff

169
drivers/net/wireless/ipw2100.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
Copyright(c) 2003 - 2005 Intel Corporation. All rights reserved.
Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of version 2 of the GNU General Public License as
@ -92,7 +92,6 @@ struct ipw2100_rx_packet;
#define IPW_DL_IOCTL (1<<14)
#define IPW_DL_RF_KILL (1<<17)
#define IPW_DL_MANAGE (1<<15)
#define IPW_DL_FW (1<<16)
@ -155,7 +154,9 @@ extern const char *band_str[];
struct bd_status {
union {
struct { u8 nlf:1, txType:2, intEnabled:1, reserved:4;} fields;
struct {
u8 nlf:1, txType:2, intEnabled:1, reserved:4;
} fields;
u8 field;
} info;
} __attribute__ ((packed));
@ -164,7 +165,7 @@ struct ipw2100_bd {
u32 host_addr;
u32 buf_length;
struct bd_status status;
/* number of fragments for frame (should be set only for
/* number of fragments for frame (should be set only for
* 1st TBD) */
u8 num_fragments;
u8 reserved[6];
@ -292,10 +293,10 @@ struct ipw2100_cmd_header {
struct ipw2100_data_header {
u32 host_command_reg;
u32 host_command_reg1;
u8 encrypted; // BOOLEAN in win! TRUE if frame is enc by driver
u8 encrypted; // BOOLEAN in win! TRUE if frame is enc by driver
u8 needs_encryption; // BOOLEAN in win! TRUE if frma need to be enc in NIC
u8 wep_index; // 0 no key, 1-4 key index, 0xff immediate key
u8 key_size; // 0 no imm key, 0x5 64bit encr, 0xd 128bit encr, 0x10 128bit encr and 128bit IV
u8 key_size; // 0 no imm key, 0x5 64bit encr, 0xd 128bit encr, 0x10 128bit encr and 128bit IV
u8 key[16];
u8 reserved[10]; // f/w reserved
u8 src_addr[ETH_ALEN];
@ -305,14 +306,13 @@ struct ipw2100_data_header {
/* Host command data structure */
struct host_command {
u32 host_command; // COMMAND ID
u32 host_command1; // COMMAND ID
u32 host_command; // COMMAND ID
u32 host_command1; // COMMAND ID
u32 host_command_sequence; // UNIQUE COMMAND NUMBER (ID)
u32 host_command_length; // LENGTH
u32 host_command_parameters[HOST_COMMAND_PARAMS_REG_LEN]; // COMMAND PARAMETERS
} __attribute__ ((packed));
typedef enum {
POWER_ON_RESET,
EXIT_POWER_DOWN_RESET,
@ -327,17 +327,16 @@ enum {
RX
};
struct ipw2100_tx_packet {
int type;
int index;
union {
struct { /* COMMAND */
struct ipw2100_cmd_header* cmd;
struct { /* COMMAND */
struct ipw2100_cmd_header *cmd;
dma_addr_t cmd_phys;
} c_struct;
struct { /* DATA */
struct ipw2100_data_header* data;
struct { /* DATA */
struct ipw2100_data_header *data;
dma_addr_t data_phys;
struct ieee80211_txb *txb;
} d_struct;
@ -347,7 +346,6 @@ struct ipw2100_tx_packet {
struct list_head list;
};
struct ipw2100_rx_packet {
struct ipw2100_rx *rxp;
dma_addr_t dma_addr;
@ -431,13 +429,13 @@ enum {
};
#define STATUS_POWERED (1<<0)
#define STATUS_CMD_ACTIVE (1<<1) /**< host command in progress */
#define STATUS_RUNNING (1<<2) /* Card initialized, but not enabled */
#define STATUS_ENABLED (1<<3) /* Card enabled -- can scan,Tx,Rx */
#define STATUS_STOPPING (1<<4) /* Card is in shutdown phase */
#define STATUS_INITIALIZED (1<<5) /* Card is ready for external calls */
#define STATUS_ASSOCIATING (1<<9) /* Associated, but no BSSID yet */
#define STATUS_ASSOCIATED (1<<10) /* Associated and BSSID valid */
#define STATUS_CMD_ACTIVE (1<<1) /**< host command in progress */
#define STATUS_RUNNING (1<<2) /* Card initialized, but not enabled */
#define STATUS_ENABLED (1<<3) /* Card enabled -- can scan,Tx,Rx */
#define STATUS_STOPPING (1<<4) /* Card is in shutdown phase */
#define STATUS_INITIALIZED (1<<5) /* Card is ready for external calls */
#define STATUS_ASSOCIATING (1<<9) /* Associated, but no BSSID yet */
#define STATUS_ASSOCIATED (1<<10) /* Associated and BSSID valid */
#define STATUS_INT_ENABLED (1<<11)
#define STATUS_RF_KILL_HW (1<<12)
#define STATUS_RF_KILL_SW (1<<13)
@ -450,9 +448,7 @@ enum {
#define STATUS_SCAN_COMPLETE (1<<26)
#define STATUS_WX_EVENT_PENDING (1<<27)
#define STATUS_RESET_PENDING (1<<29)
#define STATUS_SECURITY_UPDATED (1<<30) /* Security sync needed */
#define STATUS_SECURITY_UPDATED (1<<30) /* Security sync needed */
/* Internal NIC states */
#define IPW_STATE_INITIALIZED (1<<0)
@ -468,11 +464,9 @@ enum {
#define IPW_STATE_POWER_DOWN (1<<10)
#define IPW_STATE_SCANNING (1<<11)
#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
#define CFG_CUSTOM_MAC (1<<3)
#define CFG_LONG_PREAMBLE (1<<4)
#define CFG_ASSOCIATE (1<<6)
@ -480,14 +474,17 @@ enum {
#define CFG_ADHOC_CREATE (1<<8)
#define CFG_C3_DISABLED (1<<9)
#define CFG_PASSIVE_SCAN (1<<10)
#ifdef CONFIG_IPW2100_MONITOR
#define CFG_CRC_CHECK (1<<11)
#endif
#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
struct ipw2100_priv {
int stop_hang_check; /* Set 1 when shutting down to kill hang_check */
int stop_rf_kill; /* Set 1 when shutting down to kill rf_kill */
int stop_hang_check; /* Set 1 when shutting down to kill hang_check */
int stop_rf_kill; /* Set 1 when shutting down to kill rf_kill */
struct ieee80211_device *ieee;
unsigned long status;
@ -518,19 +515,16 @@ struct ipw2100_priv {
unsigned long hw_features;
int hangs;
u32 last_rtc;
int dump_raw; /* 1 to dump raw bytes in /sys/.../memory */
u8* snapshot[0x30];
int dump_raw; /* 1 to dump raw bytes in /sys/.../memory */
u8 *snapshot[0x30];
u8 mandatory_bssid_mac[ETH_ALEN];
u8 mac_addr[ETH_ALEN];
int power_mode;
/* WEP data */
struct ieee80211_security sec;
int messages_sent;
int short_retry_limit;
int long_retry_limit;
@ -598,7 +592,6 @@ struct ipw2100_priv {
wait_queue_head_t wait_command_queue;
};
/*********************************************************
* Host Command -> From Driver to FW
*********************************************************/
@ -645,7 +638,6 @@ struct ipw2100_priv {
#define CARD_DISABLE_PHY_OFF 61
#define MSDU_TX_RATES 62
/* Rogue AP Detection */
#define SET_STATION_STAT_BITS 64
#define CLEAR_STATIONS_STAT_BITS 65
@ -654,8 +646,6 @@ struct ipw2100_priv {
#define DISASSOCIATION_BSSID 68
#define SET_WPA_IE 69
/* system configuration bit mask: */
#define IPW_CFG_MONITOR 0x00004
#define IPW_CFG_PREAMBLE_AUTO 0x00010
@ -703,7 +693,7 @@ struct ipw2100_priv {
#define IPW2100_INTA_TX_TRANSFER (0x00000001) // Bit 0 (LSB)
#define IPW2100_INTA_RX_TRANSFER (0x00000002) // Bit 1
#define IPW2100_INTA_TX_COMPLETE (0x00000004) // Bit 2
#define IPW2100_INTA_EVENT_INTERRUPT (0x00000008) // Bit 3
#define IPW2100_INTA_EVENT_INTERRUPT (0x00000008) // Bit 3
#define IPW2100_INTA_STATUS_CHANGE (0x00000010) // Bit 4
#define IPW2100_INTA_BEACON_PERIOD_EXPIRED (0x00000020) // Bit 5
#define IPW2100_INTA_SLAVE_MODE_HOST_COMMAND_DONE (0x00010000) // Bit 16
@ -783,9 +773,6 @@ struct ipw2100_priv {
#define IPW_CARD_DISABLE_PHY_OFF_COMPLETE_WAIT 100 // 100 milli
#define IPW_PREPARE_POWER_DOWN_COMPLETE_WAIT 100 // 100 milli
#define IPW_HEADER_802_11_SIZE sizeof(struct ieee80211_hdr_3addr)
#define IPW_MAX_80211_PAYLOAD_SIZE 2304U
#define IPW_MAX_802_11_PAYLOAD_LENGTH 2312
@ -842,8 +829,8 @@ struct ipw2100_rx {
#define IPW_TX_POWER_MIN_DBM (-12)
#define IPW_TX_POWER_MAX_DBM 16
#define FW_SCAN_DONOT_ASSOCIATE 0x0001 // Dont Attempt to Associate after Scan
#define FW_SCAN_PASSIVE 0x0008 // Force PASSSIVE Scan
#define FW_SCAN_DONOT_ASSOCIATE 0x0001 // Dont Attempt to Associate after Scan
#define FW_SCAN_PASSIVE 0x0008 // Force PASSSIVE Scan
#define REG_MIN_CHANNEL 0
#define REG_MAX_CHANNEL 14
@ -855,7 +842,6 @@ struct ipw2100_rx {
#define DIVERSITY_ANTENNA_A 1 // Use antenna A
#define DIVERSITY_ANTENNA_B 2 // Use antenna B
#define HOST_COMMAND_WAIT 0
#define HOST_COMMAND_NO_WAIT 1
@ -872,10 +858,9 @@ struct ipw2100_rx {
#define TYPE_ASSOCIATION_REQUEST 0x0013
#define TYPE_REASSOCIATION_REQUEST 0x0014
#define HW_FEATURE_RFKILL (0x0001)
#define RF_KILLSWITCH_OFF (1)
#define RF_KILLSWITCH_ON (0)
#define HW_FEATURE_RFKILL 0x0001
#define RF_KILLSWITCH_OFF 1
#define RF_KILLSWITCH_ON 0
#define IPW_COMMAND_POOL_SIZE 40
@ -894,7 +879,7 @@ struct ipw2100_rx {
// Fixed size data: Ordinal Table 1
typedef enum _ORDINAL_TABLE_1 { // NS - means Not Supported by FW
// Transmit statistics
IPW_ORD_STAT_TX_HOST_REQUESTS = 1,// # of requested Host Tx's (MSDU)
IPW_ORD_STAT_TX_HOST_REQUESTS = 1, // # of requested Host Tx's (MSDU)
IPW_ORD_STAT_TX_HOST_COMPLETE, // # of successful Host Tx's (MSDU)
IPW_ORD_STAT_TX_DIR_DATA, // # of successful Directed Tx's (MSDU)
@ -904,42 +889,42 @@ typedef enum _ORDINAL_TABLE_1 { // NS - means Not Supported by FW
IPW_ORD_STAT_TX_DIR_DATA11, // # of successful Directed Tx's (MSDU) @ 11MB
IPW_ORD_STAT_TX_DIR_DATA22, // # of successful Directed Tx's (MSDU) @ 22MB
IPW_ORD_STAT_TX_NODIR_DATA1 = 13,// # of successful Non_Directed Tx's (MSDU) @ 1MB
IPW_ORD_STAT_TX_NODIR_DATA1 = 13, // # of successful Non_Directed Tx's (MSDU) @ 1MB
IPW_ORD_STAT_TX_NODIR_DATA2, // # of successful Non_Directed Tx's (MSDU) @ 2MB
IPW_ORD_STAT_TX_NODIR_DATA5_5, // # of successful Non_Directed Tx's (MSDU) @ 5.5MB
IPW_ORD_STAT_TX_NODIR_DATA11, // # of successful Non_Directed Tx's (MSDU) @ 11MB
IPW_ORD_STAT_NULL_DATA = 21, // # of successful NULL data Tx's
IPW_ORD_STAT_TX_RTS, // # of successful Tx RTS
IPW_ORD_STAT_TX_CTS, // # of successful Tx CTS
IPW_ORD_STAT_TX_ACK, // # of successful Tx ACK
IPW_ORD_STAT_TX_ASSN, // # of successful Association Tx's
IPW_ORD_STAT_TX_RTS, // # of successful Tx RTS
IPW_ORD_STAT_TX_CTS, // # of successful Tx CTS
IPW_ORD_STAT_TX_ACK, // # of successful Tx ACK
IPW_ORD_STAT_TX_ASSN, // # of successful Association Tx's
IPW_ORD_STAT_TX_ASSN_RESP, // # of successful Association response Tx's
IPW_ORD_STAT_TX_REASSN, // # of successful Reassociation Tx's
IPW_ORD_STAT_TX_REASSN, // # of successful Reassociation Tx's
IPW_ORD_STAT_TX_REASSN_RESP, // # of successful Reassociation response Tx's
IPW_ORD_STAT_TX_PROBE, // # of probes successfully transmitted
IPW_ORD_STAT_TX_PROBE, // # of probes successfully transmitted
IPW_ORD_STAT_TX_PROBE_RESP, // # of probe responses successfully transmitted
IPW_ORD_STAT_TX_BEACON, // # of tx beacon
IPW_ORD_STAT_TX_ATIM, // # of Tx ATIM
IPW_ORD_STAT_TX_BEACON, // # of tx beacon
IPW_ORD_STAT_TX_ATIM, // # of Tx ATIM
IPW_ORD_STAT_TX_DISASSN, // # of successful Disassociation TX
IPW_ORD_STAT_TX_AUTH, // # of successful Authentication Tx
IPW_ORD_STAT_TX_DEAUTH, // # of successful Deauthentication TX
IPW_ORD_STAT_TX_AUTH, // # of successful Authentication Tx
IPW_ORD_STAT_TX_DEAUTH, // # of successful Deauthentication TX
IPW_ORD_STAT_TX_TOTAL_BYTES = 41,// Total successful Tx data bytes
IPW_ORD_STAT_TX_RETRIES, // # of Tx retries
IPW_ORD_STAT_TX_RETRY1, // # of Tx retries at 1MBPS
IPW_ORD_STAT_TX_RETRY2, // # of Tx retries at 2MBPS
IPW_ORD_STAT_TX_RETRY5_5, // # of Tx retries at 5.5MBPS
IPW_ORD_STAT_TX_RETRY11, // # of Tx retries at 11MBPS
IPW_ORD_STAT_TX_TOTAL_BYTES = 41, // Total successful Tx data bytes
IPW_ORD_STAT_TX_RETRIES, // # of Tx retries
IPW_ORD_STAT_TX_RETRY1, // # of Tx retries at 1MBPS
IPW_ORD_STAT_TX_RETRY2, // # of Tx retries at 2MBPS
IPW_ORD_STAT_TX_RETRY5_5, // # of Tx retries at 5.5MBPS
IPW_ORD_STAT_TX_RETRY11, // # of Tx retries at 11MBPS
IPW_ORD_STAT_TX_FAILURES = 51, // # of Tx Failures
IPW_ORD_STAT_TX_ABORT_AT_HOP, //NS // # of Tx's aborted at hop time
IPW_ORD_STAT_TX_MAX_TRIES_IN_HOP,// # of times max tries in a hop failed
IPW_ORD_STAT_TX_MAX_TRIES_IN_HOP, // # of times max tries in a hop failed
IPW_ORD_STAT_TX_ABORT_LATE_DMA, //NS // # of times tx aborted due to late dma setup
IPW_ORD_STAT_TX_ABORT_STX, //NS // # of times backoff aborted
IPW_ORD_STAT_TX_DISASSN_FAIL, // # of times disassociation failed
IPW_ORD_STAT_TX_ERR_CTS, // # of missed/bad CTS frames
IPW_ORD_STAT_TX_BPDU, //NS // # of spanning tree BPDUs sent
IPW_ORD_STAT_TX_ERR_CTS, // # of missed/bad CTS frames
IPW_ORD_STAT_TX_BPDU, //NS // # of spanning tree BPDUs sent
IPW_ORD_STAT_TX_ERR_ACK, // # of tx err due to acks
// Receive statistics
@ -951,7 +936,7 @@ typedef enum _ORDINAL_TABLE_1 { // NS - means Not Supported by FW
IPW_ORD_STAT_RX_DIR_DATA11, // # of directed packets at 11MB
IPW_ORD_STAT_RX_DIR_DATA22, // # of directed packets at 22MB
IPW_ORD_STAT_RX_NODIR_DATA = 71,// # of nondirected packets
IPW_ORD_STAT_RX_NODIR_DATA = 71, // # of nondirected packets
IPW_ORD_STAT_RX_NODIR_DATA1, // # of nondirected packets at 1MB
IPW_ORD_STAT_RX_NODIR_DATA2, // # of nondirected packets at 2MB
IPW_ORD_STAT_RX_NODIR_DATA5_5, // # of nondirected packets at 5.5MB
@ -976,18 +961,18 @@ typedef enum _ORDINAL_TABLE_1 { // NS - means Not Supported by FW
IPW_ORD_STAT_RX_AUTH, // # of authentication Rx
IPW_ORD_STAT_RX_DEAUTH, // # of deauthentication Rx
IPW_ORD_STAT_RX_TOTAL_BYTES = 101,// Total rx data bytes received
IPW_ORD_STAT_RX_ERR_CRC, // # of packets with Rx CRC error
IPW_ORD_STAT_RX_ERR_CRC1, // # of Rx CRC errors at 1MB
IPW_ORD_STAT_RX_ERR_CRC2, // # of Rx CRC errors at 2MB
IPW_ORD_STAT_RX_ERR_CRC5_5, // # of Rx CRC errors at 5.5MB
IPW_ORD_STAT_RX_ERR_CRC11, // # of Rx CRC errors at 11MB
IPW_ORD_STAT_RX_TOTAL_BYTES = 101, // Total rx data bytes received
IPW_ORD_STAT_RX_ERR_CRC, // # of packets with Rx CRC error
IPW_ORD_STAT_RX_ERR_CRC1, // # of Rx CRC errors at 1MB
IPW_ORD_STAT_RX_ERR_CRC2, // # of Rx CRC errors at 2MB
IPW_ORD_STAT_RX_ERR_CRC5_5, // # of Rx CRC errors at 5.5MB
IPW_ORD_STAT_RX_ERR_CRC11, // # of Rx CRC errors at 11MB
IPW_ORD_STAT_RX_DUPLICATE1 = 112, // # of duplicate rx packets at 1MB
IPW_ORD_STAT_RX_DUPLICATE2, // # of duplicate rx packets at 2MB
IPW_ORD_STAT_RX_DUPLICATE5_5, // # of duplicate rx packets at 5.5MB
IPW_ORD_STAT_RX_DUPLICATE11, // # of duplicate rx packets at 11MB
IPW_ORD_STAT_RX_DUPLICATE = 119, // # of duplicate rx packets
IPW_ORD_STAT_RX_DUPLICATE1 = 112, // # of duplicate rx packets at 1MB
IPW_ORD_STAT_RX_DUPLICATE2, // # of duplicate rx packets at 2MB
IPW_ORD_STAT_RX_DUPLICATE5_5, // # of duplicate rx packets at 5.5MB
IPW_ORD_STAT_RX_DUPLICATE11, // # of duplicate rx packets at 11MB
IPW_ORD_STAT_RX_DUPLICATE = 119, // # of duplicate rx packets
IPW_ORD_PERS_DB_LOCK = 120, // # locking fw permanent db
IPW_ORD_PERS_DB_SIZE, // # size of fw permanent db
@ -1005,17 +990,17 @@ typedef enum _ORDINAL_TABLE_1 { // NS - means Not Supported by FW
IPW_ORD_STAT_RX_ICV_ERRORS, // # of ICV errors during decryption
// PSP Statistics
IPW_ORD_STAT_PSP_SUSPENSION = 137,// # of times adapter suspended
IPW_ORD_STAT_PSP_SUSPENSION = 137, // # of times adapter suspended
IPW_ORD_STAT_PSP_BCN_TIMEOUT, // # of beacon timeout
IPW_ORD_STAT_PSP_POLL_TIMEOUT, // # of poll response timeouts
IPW_ORD_STAT_PSP_NONDIR_TIMEOUT,// # of timeouts waiting for last broadcast/muticast pkt
IPW_ORD_STAT_PSP_NONDIR_TIMEOUT, // # of timeouts waiting for last broadcast/muticast pkt
IPW_ORD_STAT_PSP_RX_DTIMS, // # of PSP DTIMs received
IPW_ORD_STAT_PSP_RX_TIMS, // # of PSP TIMs received
IPW_ORD_STAT_PSP_STATION_ID, // PSP Station ID
// Association and roaming
IPW_ORD_LAST_ASSN_TIME = 147, // RTC time of last association
IPW_ORD_STAT_PERCENT_MISSED_BCNS,// current calculation of % missed beacons
IPW_ORD_STAT_PERCENT_MISSED_BCNS, // current calculation of % missed beacons
IPW_ORD_STAT_PERCENT_RETRIES, // current calculation of % missed tx retries
IPW_ORD_ASSOCIATED_AP_PTR, // If associated, this is ptr to the associated
// AP table entry. set to 0 if not associated
@ -1150,7 +1135,7 @@ struct ipw2100_fw_chunk {
};
struct ipw2100_fw_chunk_set {
const void *data;
const void *data;
unsigned long size;
};
@ -1163,4 +1148,4 @@ struct ipw2100_fw {
#define MAX_FW_VERSION_LEN 14
#endif /* _IPW2100_H */
#endif /* _IPW2100_H */

6621
drivers/net/wireless/ipw2200.c
View file

File diff suppressed because it is too large Load diff

566
drivers/net/wireless/ipw2200.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
Copyright(c) 2003 - 2005 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of version 2 of the GNU General Public License as
@ -49,6 +49,7 @@
#include <asm/io.h>
#include <net/ieee80211.h>
#include <net/ieee80211_radiotap.h>
#define DRV_NAME "ipw2200"
@ -160,6 +161,16 @@ enum connection_manager_assoc_states {
* TX Queue Flag Definitions
*/
/* tx wep key definition */
#define DCT_WEP_KEY_NOT_IMMIDIATE 0x00
#define DCT_WEP_KEY_64Bit 0x40
#define DCT_WEP_KEY_128Bit 0x80
#define DCT_WEP_KEY_128bitIV 0xC0
#define DCT_WEP_KEY_SIZE_MASK 0xC0
#define DCT_WEP_KEY_INDEX_MASK 0x0F
#define DCT_WEP_INDEX_USE_IMMEDIATE 0x20
/* abort attempt if mgmt frame is rx'd */
#define DCT_FLAG_ABORT_MGMT 0x01
@ -167,7 +178,8 @@ enum connection_manager_assoc_states {
#define DCT_FLAG_CTS_REQUIRED 0x02
/* use short preamble */
#define DCT_FLAG_SHORT_PREMBL 0x04
#define DCT_FLAG_LONG_PREAMBLE 0x00
#define DCT_FLAG_SHORT_PREAMBLE 0x04
/* RTS/CTS first */
#define DCT_FLAG_RTS_REQD 0x08
@ -184,9 +196,23 @@ enum connection_manager_assoc_states {
/* ACK rx is expected to follow */
#define DCT_FLAG_ACK_REQD 0x80
/* TX flags extension */
#define DCT_FLAG_EXT_MODE_CCK 0x01
#define DCT_FLAG_EXT_MODE_OFDM 0x00
#define DCT_FLAG_EXT_SECURITY_WEP 0x00
#define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP
#define DCT_FLAG_EXT_SECURITY_CKIP 0x04
#define DCT_FLAG_EXT_SECURITY_CCM 0x08
#define DCT_FLAG_EXT_SECURITY_TKIP 0x0C
#define DCT_FLAG_EXT_SECURITY_MASK 0x0C
#define DCT_FLAG_EXT_QOS_ENABLED 0x10
#define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00
#define DCT_FLAG_EXT_HC_SIFS 0x20
#define DCT_FLAG_EXT_HC_PIFS 0x40
#define TX_RX_TYPE_MASK 0xFF
#define TX_FRAME_TYPE 0x00
#define TX_HOST_COMMAND_TYPE 0x01
@ -232,6 +258,117 @@ enum connection_manager_assoc_states {
#define DCR_TYPE_SNIFFER 0x06
#define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
/* QoS definitions */
#define CW_MIN_OFDM 15
#define CW_MAX_OFDM 1023
#define CW_MIN_CCK 31
#define CW_MAX_CCK 1023
#define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
#define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
#define QOS_TX2_CW_MIN_OFDM ( (CW_MIN_OFDM + 1) / 2 - 1 )
#define QOS_TX3_CW_MIN_OFDM ( (CW_MIN_OFDM + 1) / 4 - 1 )
#define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
#define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
#define QOS_TX2_CW_MIN_CCK ( (CW_MIN_CCK + 1) / 2 - 1 )
#define QOS_TX3_CW_MIN_CCK ( (CW_MIN_CCK + 1) / 4 - 1 )
#define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
#define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
#define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
#define QOS_TX3_CW_MAX_OFDM ( (CW_MIN_OFDM + 1) / 2 - 1 )
#define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
#define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
#define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
#define QOS_TX3_CW_MAX_CCK ( (CW_MIN_CCK + 1) / 2 - 1 )
#define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE)
#define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE)
#define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE)
#define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE)
#define QOS_TX0_ACM 0
#define QOS_TX1_ACM 0
#define QOS_TX2_ACM 0
#define QOS_TX3_ACM 0
#define QOS_TX0_TXOP_LIMIT_CCK 0
#define QOS_TX1_TXOP_LIMIT_CCK 0
#define QOS_TX2_TXOP_LIMIT_CCK 6016
#define QOS_TX3_TXOP_LIMIT_CCK 3264
#define QOS_TX0_TXOP_LIMIT_OFDM 0
#define QOS_TX1_TXOP_LIMIT_OFDM 0
#define QOS_TX2_TXOP_LIMIT_OFDM 3008
#define QOS_TX3_TXOP_LIMIT_OFDM 1504
#define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
#define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
#define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
#define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
#define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
#define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
#define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
#define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
#define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
#define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
#define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
#define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
#define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
#define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
#define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
#define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
#define DEF_TX0_AIFS 0
#define DEF_TX1_AIFS 0
#define DEF_TX2_AIFS 0
#define DEF_TX3_AIFS 0
#define DEF_TX0_ACM 0
#define DEF_TX1_ACM 0
#define DEF_TX2_ACM 0
#define DEF_TX3_ACM 0
#define DEF_TX0_TXOP_LIMIT_CCK 0
#define DEF_TX1_TXOP_LIMIT_CCK 0
#define DEF_TX2_TXOP_LIMIT_CCK 0
#define DEF_TX3_TXOP_LIMIT_CCK 0
#define DEF_TX0_TXOP_LIMIT_OFDM 0
#define DEF_TX1_TXOP_LIMIT_OFDM 0
#define DEF_TX2_TXOP_LIMIT_OFDM 0
#define DEF_TX3_TXOP_LIMIT_OFDM 0
#define QOS_QOS_SETS 3
#define QOS_PARAM_SET_ACTIVE 0
#define QOS_PARAM_SET_DEF_CCK 1
#define QOS_PARAM_SET_DEF_OFDM 2
#define CTRL_QOS_NO_ACK (0x0020)
#define IPW_TX_QUEUE_1 1
#define IPW_TX_QUEUE_2 2
#define IPW_TX_QUEUE_3 3
#define IPW_TX_QUEUE_4 4
/* QoS sturctures */
struct ipw_qos_info {
int qos_enable;
struct ieee80211_qos_parameters *def_qos_parm_OFDM;
struct ieee80211_qos_parameters *def_qos_parm_CCK;
u32 burst_duration_CCK;
u32 burst_duration_OFDM;
u16 qos_no_ack_mask;
int burst_enable;
};
/**************************************************************/
/**
* Generic queue structure
*
@ -401,9 +538,9 @@ struct clx2_tx_queue {
#define RX_FREE_BUFFERS 32
#define RX_LOW_WATERMARK 8
#define SUP_RATE_11A_MAX_NUM_CHANNELS (8)
#define SUP_RATE_11B_MAX_NUM_CHANNELS (4)
#define SUP_RATE_11G_MAX_NUM_CHANNELS (12)
#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
// Used for passing to driver number of successes and failures per rate
struct rate_histogram {
@ -452,6 +589,9 @@ struct notif_channel_result {
u8 uReserved;
} __attribute__ ((packed));
#define SCAN_COMPLETED_STATUS_COMPLETE 1
#define SCAN_COMPLETED_STATUS_ABORTED 2
struct notif_scan_complete {
u8 scan_type;
u8 num_channels;
@ -562,8 +702,8 @@ struct ipw_rx_packet {
} __attribute__ ((packed));
#define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
#define IPW_RX_FRAME_SIZE sizeof(struct ipw_rx_header) + \
sizeof(struct ipw_rx_frame)
#define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \
sizeof(struct ipw_rx_frame))
struct ipw_rx_mem_buffer {
dma_addr_t dma_addr;
@ -656,6 +796,19 @@ struct ipw_multicast_addr {
u8 mac4[6];
} __attribute__ ((packed));
#define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */
#define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */
#define DCW_WEP_KEY_SEC_TYPE_WEP 0x00
#define DCW_WEP_KEY_SEC_TYPE_CCM 0x20
#define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30
#define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */
#define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */
#define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */
#define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */
//#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */
struct ipw_wep_key {
u8 cmd_id;
u8 seq_num;
@ -817,14 +970,6 @@ struct ipw_tx_power {
struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
} __attribute__ ((packed));
struct ipw_qos_parameters {
u16 cw_min[4];
u16 cw_max[4];
u8 aifs[4];
u8 flag[4];
u16 tx_op_limit[4];
} __attribute__ ((packed));
struct ipw_rsn_capabilities {
u8 id;
u8 length;
@ -887,6 +1032,10 @@ struct ipw_cmd {
#define STATUS_SCAN_PENDING (1<<20)
#define STATUS_SCANNING (1<<21)
#define STATUS_SCAN_ABORTING (1<<22)
#define STATUS_SCAN_FORCED (1<<23)
#define STATUS_LED_LINK_ON (1<<24)
#define STATUS_LED_ACT_ON (1<<25)
#define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
#define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
@ -898,11 +1047,15 @@ struct ipw_cmd {
#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
#define CFG_CUSTOM_MAC (1<<3)
#define CFG_PREAMBLE (1<<4)
#define CFG_PREAMBLE_LONG (1<<4)
#define CFG_ADHOC_PERSIST (1<<5)
#define CFG_ASSOCIATE (1<<6)
#define CFG_FIXED_RATE (1<<7)
#define CFG_ADHOC_CREATE (1<<8)
#define CFG_NO_LED (1<<9)
#define CFG_BACKGROUND_SCAN (1<<10)
#define CFG_SPEED_SCAN (1<<11)
#define CFG_NET_STATS (1<<12)
#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
@ -924,13 +1077,50 @@ struct average {
s32 sum;
};
#define MAX_SPEED_SCAN 100
#define IPW_IBSS_MAC_HASH_SIZE 31
struct ipw_ibss_seq {
u8 mac[ETH_ALEN];
u16 seq_num;
u16 frag_num;
unsigned long packet_time;
struct list_head list;
};
struct ipw_error_elem {
u32 desc;
u32 time;
u32 blink1;
u32 blink2;
u32 link1;
u32 link2;
u32 data;
};
struct ipw_event {
u32 event;
u32 time;
u32 data;
} __attribute__ ((packed));
struct ipw_fw_error {
unsigned long jiffies;
u32 status;
u32 config;
u32 elem_len;
u32 log_len;
struct ipw_error_elem *elem;
struct ipw_event *log;
u8 payload[0];
} __attribute__ ((packed));
struct ipw_priv {
/* ieee device used by generic ieee processing code */
struct ieee80211_device *ieee;
struct ieee80211_security sec;
/* spinlock */
spinlock_t lock;
struct semaphore sem;
/* basic pci-network driver stuff */
struct pci_dev *pci_dev;
@ -965,7 +1155,7 @@ struct ipw_priv {
int rx_bufs_min; /**< minimum number of bufs in Rx queue */
int rx_pend_max; /**< maximum pending buffers for one IRQ */
u32 hcmd_seq; /**< sequence number for hcmd */
u32 missed_beacon_threshold;
u32 disassociate_threshold;
u32 roaming_threshold;
struct ipw_associate assoc_request;
@ -1006,6 +1196,8 @@ struct ipw_priv {
u8 mac_addr[ETH_ALEN];
u8 num_stations;
u8 stations[MAX_STATIONS][ETH_ALEN];
u8 short_retry_limit;
u8 long_retry_limit;
u32 notif_missed_beacons;
@ -1023,17 +1215,29 @@ struct ipw_priv {
u32 tx_packets;
u32 quality;
u8 speed_scan[MAX_SPEED_SCAN];
u8 speed_scan_pos;
u16 last_seq_num;
u16 last_frag_num;
unsigned long last_packet_time;
struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE];
/* eeprom */
u8 eeprom[0x100]; /* 256 bytes of eeprom */
u8 country[4];
int eeprom_delay;
struct iw_statistics wstats;
struct iw_public_data wireless_data;
struct workqueue_struct *workqueue;
struct work_struct adhoc_check;
struct work_struct associate;
struct work_struct disassociate;
struct work_struct system_config;
struct work_struct rx_replenish;
struct work_struct request_scan;
struct work_struct adapter_restart;
@ -1044,25 +1248,51 @@ struct ipw_priv {
struct work_struct abort_scan;
struct work_struct roam;
struct work_struct scan_check;
struct work_struct link_up;
struct work_struct link_down;
struct tasklet_struct irq_tasklet;
/* LED related variables and work_struct */
u8 nic_type;
u32 led_activity_on;
u32 led_activity_off;
u32 led_association_on;
u32 led_association_off;
u32 led_ofdm_on;
u32 led_ofdm_off;
struct work_struct led_link_on;
struct work_struct led_link_off;
struct work_struct led_act_off;
struct work_struct merge_networks;
struct ipw_cmd_log *cmdlog;
int cmdlog_len;
int cmdlog_pos;
#define IPW_2200BG 1
#define IPW_2915ABG 2
u8 adapter;
#define IPW_DEFAULT_TX_POWER 0x14
u8 tx_power;
s8 tx_power;
#ifdef CONFIG_PM
u32 pm_state[16];
#endif
struct ipw_fw_error *error;
/* network state */
/* Used to pass the current INTA value from ISR to Tasklet */
u32 isr_inta;
/* QoS */
struct ipw_qos_info qos_data;
struct work_struct qos_activate;
/*********************************/
/* debugging info */
u32 indirect_dword;
u32 direct_dword;
@ -1124,6 +1354,8 @@ do { if (ipw_debug_level & (level)) \
#define IPW_DL_RF_KILL (1<<17)
#define IPW_DL_FW_ERRORS (1<<18)
#define IPW_DL_LED (1<<19)
#define IPW_DL_ORD (1<<20)
#define IPW_DL_FRAG (1<<21)
@ -1136,6 +1368,8 @@ do { if (ipw_debug_level & (level)) \
#define IPW_DL_TRACE (1<<28)
#define IPW_DL_STATS (1<<29)
#define IPW_DL_MERGE (1<<30)
#define IPW_DL_QOS (1<<31)
#define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
#define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
@ -1149,6 +1383,7 @@ do { if (ipw_debug_level & (level)) \
#define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a)
#define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a)
#define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
#define IPW_DEBUG_LED(f, a...) IPW_DEBUG(IPW_DL_LED, f, ## a)
#define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a)
#define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
#define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a)
@ -1162,6 +1397,8 @@ do { if (ipw_debug_level & (level)) \
#define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
#define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
#define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a)
#define IPW_DEBUG_MERGE(f, a...) IPW_DEBUG(IPW_DL_MERGE, f, ## a)
#define IPW_DEBUG_QOS(f, a...) IPW_DEBUG(IPW_DL_QOS, f, ## a)
#include <linux/ctype.h>
@ -1176,59 +1413,65 @@ do { if (ipw_debug_level & (level)) \
#define DINO_RXFIFO_DATA 0x01
#define DINO_CONTROL_REG 0x00200000
#define CX2_INTA_RW 0x00000008
#define CX2_INTA_MASK_R 0x0000000C
#define CX2_INDIRECT_ADDR 0x00000010
#define CX2_INDIRECT_DATA 0x00000014
#define CX2_AUTOINC_ADDR 0x00000018
#define CX2_AUTOINC_DATA 0x0000001C
#define CX2_RESET_REG 0x00000020
#define CX2_GP_CNTRL_RW 0x00000024
#define IPW_INTA_RW 0x00000008
#define IPW_INTA_MASK_R 0x0000000C
#define IPW_INDIRECT_ADDR 0x00000010
#define IPW_INDIRECT_DATA 0x00000014
#define IPW_AUTOINC_ADDR 0x00000018
#define IPW_AUTOINC_DATA 0x0000001C
#define IPW_RESET_REG 0x00000020
#define IPW_GP_CNTRL_RW 0x00000024
#define CX2_READ_INT_REGISTER 0xFF4
#define IPW_READ_INT_REGISTER 0xFF4
#define CX2_GP_CNTRL_BIT_INIT_DONE 0x00000004
#define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004
#define CX2_REGISTER_DOMAIN1_END 0x00001000
#define CX2_SRAM_READ_INT_REGISTER 0x00000ff4
#define IPW_REGISTER_DOMAIN1_END 0x00001000
#define IPW_SRAM_READ_INT_REGISTER 0x00000ff4
#define CX2_SHARED_LOWER_BOUND 0x00000200
#define CX2_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
#define IPW_SHARED_LOWER_BOUND 0x00000200
#define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
#define CX2_NIC_SRAM_LOWER_BOUND 0x00000000
#define CX2_NIC_SRAM_UPPER_BOUND 0x00030000
#define IPW_NIC_SRAM_LOWER_BOUND 0x00000000
#define IPW_NIC_SRAM_UPPER_BOUND 0x00030000
#define CX2_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
#define CX2_GP_CNTRL_BIT_CLOCK_READY 0x00000001
#define CX2_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
#define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
#define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001
#define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
/*
* RESET Register Bit Indexes
*/
#define CBD_RESET_REG_PRINCETON_RESET 0x00000001 /* Bit 0 (LSB) */
#define CX2_RESET_REG_SW_RESET 0x00000080 /* Bit 7 */
#define CX2_RESET_REG_MASTER_DISABLED 0x00000100 /* Bit 8 */
#define CX2_RESET_REG_STOP_MASTER 0x00000200 /* Bit 9 */
#define CX2_ARC_KESHET_CONFIG 0x08000000 /* Bit 27 */
#define CX2_START_STANDBY 0x00000004 /* Bit 2 */
#define CBD_RESET_REG_PRINCETON_RESET (1<<0)
#define IPW_START_STANDBY (1<<2)
#define IPW_ACTIVITY_LED (1<<4)
#define IPW_ASSOCIATED_LED (1<<5)
#define IPW_OFDM_LED (1<<6)
#define IPW_RESET_REG_SW_RESET (1<<7)
#define IPW_RESET_REG_MASTER_DISABLED (1<<8)
#define IPW_RESET_REG_STOP_MASTER (1<<9)
#define IPW_GATE_ODMA (1<<25)
#define IPW_GATE_IDMA (1<<26)
#define IPW_ARC_KESHET_CONFIG (1<<27)
#define IPW_GATE_ADMA (1<<29)
#define CX2_CSR_CIS_UPPER_BOUND 0x00000200
#define CX2_DOMAIN_0_END 0x1000
#define IPW_CSR_CIS_UPPER_BOUND 0x00000200
#define IPW_DOMAIN_0_END 0x1000
#define CLX_MEM_BAR_SIZE 0x1000
#define CX2_BASEBAND_CONTROL_STATUS 0X00200000
#define CX2_BASEBAND_TX_FIFO_WRITE 0X00200004
#define CX2_BASEBAND_RX_FIFO_READ 0X00200004
#define CX2_BASEBAND_CONTROL_STORE 0X00200010
#define IPW_BASEBAND_CONTROL_STATUS 0X00200000
#define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
#define IPW_BASEBAND_RX_FIFO_READ 0X00200004
#define IPW_BASEBAND_CONTROL_STORE 0X00200010
#define CX2_INTERNAL_CMD_EVENT 0X00300004
#define CX2_BASEBAND_POWER_DOWN 0x00000001
#define IPW_INTERNAL_CMD_EVENT 0X00300004
#define IPW_BASEBAND_POWER_DOWN 0x00000001
#define CX2_MEM_HALT_AND_RESET 0x003000e0
#define IPW_MEM_HALT_AND_RESET 0x003000e0
/* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
#define CX2_BIT_HALT_RESET_ON 0x80000000
#define CX2_BIT_HALT_RESET_OFF 0x00000000
#define IPW_BIT_HALT_RESET_ON 0x80000000
#define IPW_BIT_HALT_RESET_OFF 0x00000000
#define CB_LAST_VALID 0x20000000
#define CB_INT_ENABLED 0x40000000
@ -1247,63 +1490,63 @@ do { if (ipw_debug_level & (level)) \
#define DMA_CB_STOP_AND_ABORT 0x00000C00
#define DMA_CB_START 0x00000100
#define CX2_SHARED_SRAM_SIZE 0x00030000
#define CX2_SHARED_SRAM_DMA_CONTROL 0x00027000
#define IPW_SHARED_SRAM_SIZE 0x00030000
#define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000
#define CB_MAX_LENGTH 0x1FFF
#define CX2_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
#define CX2_EEPROM_IMAGE_SIZE 0x100
#define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
#define IPW_EEPROM_IMAGE_SIZE 0x100
/* DMA defs */
#define CX2_DMA_I_CURRENT_CB 0x003000D0
#define CX2_DMA_O_CURRENT_CB 0x003000D4
#define CX2_DMA_I_DMA_CONTROL 0x003000A4
#define CX2_DMA_I_CB_BASE 0x003000A0
#define IPW_DMA_I_CURRENT_CB 0x003000D0
#define IPW_DMA_O_CURRENT_CB 0x003000D4
#define IPW_DMA_I_DMA_CONTROL 0x003000A4
#define IPW_DMA_I_CB_BASE 0x003000A0
#define CX2_TX_CMD_QUEUE_BD_BASE (0x00000200)
#define CX2_TX_CMD_QUEUE_BD_SIZE (0x00000204)
#define CX2_TX_QUEUE_0_BD_BASE (0x00000208)
#define CX2_TX_QUEUE_0_BD_SIZE (0x0000020C)
#define CX2_TX_QUEUE_1_BD_BASE (0x00000210)
#define CX2_TX_QUEUE_1_BD_SIZE (0x00000214)
#define CX2_TX_QUEUE_2_BD_BASE (0x00000218)
#define CX2_TX_QUEUE_2_BD_SIZE (0x0000021C)
#define CX2_TX_QUEUE_3_BD_BASE (0x00000220)
#define CX2_TX_QUEUE_3_BD_SIZE (0x00000224)
#define CX2_RX_BD_BASE (0x00000240)
#define CX2_RX_BD_SIZE (0x00000244)
#define CX2_RFDS_TABLE_LOWER (0x00000500)
#define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200
#define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204
#define IPW_TX_QUEUE_0_BD_BASE 0x00000208
#define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C)
#define IPW_TX_QUEUE_1_BD_BASE 0x00000210
#define IPW_TX_QUEUE_1_BD_SIZE 0x00000214
#define IPW_TX_QUEUE_2_BD_BASE 0x00000218
#define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C)
#define IPW_TX_QUEUE_3_BD_BASE 0x00000220
#define IPW_TX_QUEUE_3_BD_SIZE 0x00000224
#define IPW_RX_BD_BASE 0x00000240
#define IPW_RX_BD_SIZE 0x00000244
#define IPW_RFDS_TABLE_LOWER 0x00000500
#define CX2_TX_CMD_QUEUE_READ_INDEX (0x00000280)
#define CX2_TX_QUEUE_0_READ_INDEX (0x00000284)
#define CX2_TX_QUEUE_1_READ_INDEX (0x00000288)
#define CX2_TX_QUEUE_2_READ_INDEX (0x0000028C)
#define CX2_TX_QUEUE_3_READ_INDEX (0x00000290)
#define CX2_RX_READ_INDEX (0x000002A0)
#define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280
#define IPW_TX_QUEUE_0_READ_INDEX 0x00000284
#define IPW_TX_QUEUE_1_READ_INDEX 0x00000288
#define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C)
#define IPW_TX_QUEUE_3_READ_INDEX 0x00000290
#define IPW_RX_READ_INDEX (0x000002A0)
#define CX2_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
#define CX2_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
#define CX2_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
#define CX2_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
#define CX2_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
#define CX2_RX_WRITE_INDEX (0x00000FA0)
#define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
#define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
#define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
#define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
#define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
#define IPW_RX_WRITE_INDEX (0x00000FA0)
/*
* EEPROM Related Definitions
*/
#define IPW_EEPROM_DATA_SRAM_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x814)
#define IPW_EEPROM_DATA_SRAM_SIZE (CX2_SHARED_LOWER_BOUND + 0x818)
#define IPW_EEPROM_LOAD_DISABLE (CX2_SHARED_LOWER_BOUND + 0x81C)
#define IPW_EEPROM_DATA (CX2_SHARED_LOWER_BOUND + 0x820)
#define IPW_EEPROM_UPPER_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x9E0)
#define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)
#define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818)
#define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C)
#define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820)
#define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0)
#define IPW_STATION_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0xA0C)
#define IPW_STATION_TABLE_UPPER (CX2_SHARED_LOWER_BOUND + 0xB0C)
#define IPW_REQUEST_ATIM (CX2_SHARED_LOWER_BOUND + 0xB0C)
#define IPW_ATIM_SENT (CX2_SHARED_LOWER_BOUND + 0xB10)
#define IPW_WHO_IS_AWAKE (CX2_SHARED_LOWER_BOUND + 0xB14)
#define IPW_DURING_ATIM_WINDOW (CX2_SHARED_LOWER_BOUND + 0xB18)
#define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C)
#define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C)
#define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C)
#define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10)
#define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14)
#define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18)
#define MSB 1
#define LSB 0
@ -1325,15 +1568,15 @@ do { if (ipw_debug_level & (level)) \
#define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
/* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/
#define EEPROM_NIC_TYPE_STANDARD 0
#define EEPROM_NIC_TYPE_DELL 1
#define EEPROM_NIC_TYPE_FUJITSU 2
#define EEPROM_NIC_TYPE_IBM 3
#define EEPROM_NIC_TYPE_HP 4
#define EEPROM_NIC_TYPE_0 0
#define EEPROM_NIC_TYPE_1 1
#define EEPROM_NIC_TYPE_2 2
#define EEPROM_NIC_TYPE_3 3
#define EEPROM_NIC_TYPE_4 4
#define FW_MEM_REG_LOWER_BOUND 0x00300000
#define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
#define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)
#define EEPROM_BIT_SK (1<<0)
#define EEPROM_BIT_CS (1<<1)
#define EEPROM_BIT_DI (1<<2)
@ -1342,50 +1585,47 @@ do { if (ipw_debug_level & (level)) \
#define EEPROM_CMD_READ 0x2
/* Interrupts masks */
#define CX2_INTA_NONE 0x00000000
#define IPW_INTA_NONE 0x00000000
#define CX2_INTA_BIT_RX_TRANSFER 0x00000002
#define CX2_INTA_BIT_STATUS_CHANGE 0x00000010
#define CX2_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
#define IPW_INTA_BIT_RX_TRANSFER 0x00000002
#define IPW_INTA_BIT_STATUS_CHANGE 0x00000010
#define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
//Inta Bits for CF
#define CX2_INTA_BIT_TX_CMD_QUEUE 0x00000800
#define CX2_INTA_BIT_TX_QUEUE_1 0x00001000
#define CX2_INTA_BIT_TX_QUEUE_2 0x00002000
#define CX2_INTA_BIT_TX_QUEUE_3 0x00004000
#define CX2_INTA_BIT_TX_QUEUE_4 0x00008000
#define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800
#define IPW_INTA_BIT_TX_QUEUE_1 0x00001000
#define IPW_INTA_BIT_TX_QUEUE_2 0x00002000
#define IPW_INTA_BIT_TX_QUEUE_3 0x00004000
#define IPW_INTA_BIT_TX_QUEUE_4 0x00008000
#define CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
#define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
#define CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
#define CX2_INTA_BIT_POWER_DOWN 0x00200000
#define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
#define IPW_INTA_BIT_POWER_DOWN 0x00200000
#define CX2_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
#define CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
#define CX2_INTA_BIT_RF_KILL_DONE 0x04000000
#define CX2_INTA_BIT_FATAL_ERROR 0x40000000
#define CX2_INTA_BIT_PARITY_ERROR 0x80000000
#define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
#define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
#define IPW_INTA_BIT_RF_KILL_DONE 0x04000000
#define IPW_INTA_BIT_FATAL_ERROR 0x40000000
#define IPW_INTA_BIT_PARITY_ERROR 0x80000000
/* Interrupts enabled at init time. */
#define CX2_INTA_MASK_ALL \
(CX2_INTA_BIT_TX_QUEUE_1 | \
CX2_INTA_BIT_TX_QUEUE_2 | \
CX2_INTA_BIT_TX_QUEUE_3 | \
CX2_INTA_BIT_TX_QUEUE_4 | \
CX2_INTA_BIT_TX_CMD_QUEUE | \
CX2_INTA_BIT_RX_TRANSFER | \
CX2_INTA_BIT_FATAL_ERROR | \
CX2_INTA_BIT_PARITY_ERROR | \
CX2_INTA_BIT_STATUS_CHANGE | \
CX2_INTA_BIT_FW_INITIALIZATION_DONE | \
CX2_INTA_BIT_BEACON_PERIOD_EXPIRED | \
CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
CX2_INTA_BIT_POWER_DOWN | \
CX2_INTA_BIT_RF_KILL_DONE )
#define IPWSTATUS_ERROR_LOG (CX2_SHARED_LOWER_BOUND + 0x410)
#define IPW_EVENT_LOG (CX2_SHARED_LOWER_BOUND + 0x414)
#define IPW_INTA_MASK_ALL \
(IPW_INTA_BIT_TX_QUEUE_1 | \
IPW_INTA_BIT_TX_QUEUE_2 | \
IPW_INTA_BIT_TX_QUEUE_3 | \
IPW_INTA_BIT_TX_QUEUE_4 | \
IPW_INTA_BIT_TX_CMD_QUEUE | \
IPW_INTA_BIT_RX_TRANSFER | \
IPW_INTA_BIT_FATAL_ERROR | \
IPW_INTA_BIT_PARITY_ERROR | \
IPW_INTA_BIT_STATUS_CHANGE | \
IPW_INTA_BIT_FW_INITIALIZATION_DONE | \
IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \
IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
IPW_INTA_BIT_POWER_DOWN | \
IPW_INTA_BIT_RF_KILL_DONE )
/* FW event log definitions */
#define EVENT_ELEM_SIZE (3 * sizeof(u32))
@ -1395,6 +1635,11 @@ do { if (ipw_debug_level & (level)) \
#define ERROR_ELEM_SIZE (7 * sizeof(u32))
#define ERROR_START_OFFSET (1 * sizeof(u32))
/* TX power level (dbm) */
#define IPW_TX_POWER_MIN -12
#define IPW_TX_POWER_MAX 20
#define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX
enum {
IPW_FW_ERROR_OK = 0,
IPW_FW_ERROR_FAIL,
@ -1407,8 +1652,8 @@ enum {
IPW_FW_ERROR_ALLOC_FAIL,
IPW_FW_ERROR_DMA_UNDERRUN,
IPW_FW_ERROR_DMA_STATUS,
IPW_FW_ERROR_DINOSTATUS_ERROR,
IPW_FW_ERROR_EEPROMSTATUS_ERROR,
IPW_FW_ERROR_DINO_ERROR,
IPW_FW_ERROR_EEPROM_ERROR,
IPW_FW_ERROR_SYSASSERT,
IPW_FW_ERROR_FATAL_ERROR
};
@ -1424,6 +1669,8 @@ enum {
#define HC_IBSS_RECONF 4
#define HC_DISASSOC_QUIET 5
#define HC_QOS_SUPPORT_ASSOC 0x01
#define IPW_RATE_CAPABILITIES 1
#define IPW_RATE_CONNECT 0
@ -1594,18 +1841,20 @@ enum {
IPW_ORD_TABLE_7_LAST
};
#define IPW_ORDINALS_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0x500)
#define IPW_ORDINALS_TABLE_0 (CX2_SHARED_LOWER_BOUND + 0x180)
#define IPW_ORDINALS_TABLE_1 (CX2_SHARED_LOWER_BOUND + 0x184)
#define IPW_ORDINALS_TABLE_2 (CX2_SHARED_LOWER_BOUND + 0x188)
#define IPW_MEM_FIXED_OVERRIDE (CX2_SHARED_LOWER_BOUND + 0x41C)
#define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410)
#define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414)
#define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500)
#define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180)
#define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184)
#define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188)
#define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C)
struct ipw_fixed_rate {
u16 tx_rates;
u16 reserved;
} __attribute__ ((packed));
#define CX2_INDIRECT_ADDR_MASK (~0x3ul)
#define IPW_INDIRECT_ADDR_MASK (~0x3ul)
struct host_cmd {
u8 cmd;
@ -1614,6 +1863,12 @@ struct host_cmd {
u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
} __attribute__ ((packed));
struct ipw_cmd_log {
unsigned long jiffies;
int retcode;
struct host_cmd cmd;
};
#define CFG_BT_COEXISTENCE_MIN 0x00
#define CFG_BT_COEXISTENCE_DEFER 0x02
#define CFG_BT_COEXISTENCE_KILL 0x04
@ -1642,15 +1897,6 @@ struct host_cmd {
#define REG_CHANNEL_MASK 0x00003FFF
#define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
static const long ipw_frequencies[] = {
2412, 2417, 2422, 2427,
2432, 2437, 2442, 2447,
2452, 2457, 2462, 2467,
2472, 2484
};
#define FREQ_COUNT ARRAY_SIZE(ipw_frequencies)
#define IPW_MAX_CONFIG_RETRIES 10
static inline u32 frame_hdr_len(struct ieee80211_hdr_4addr *hdr)

12
drivers/net/wireless/prism54/isl_38xx.c
View file

@ -111,9 +111,10 @@ isl38xx_handle_wakeup(isl38xx_control_block *control_block,
void
isl38xx_trigger_device(int asleep, void __iomem *device_base)
{
u32 reg, counter = 0;
u32 reg;
#if VERBOSE > SHOW_ERROR_MESSAGES
u32 counter = 0;
struct timeval current_time;
DEBUG(SHOW_FUNCTION_CALLS, "isl38xx trigger device\n");
#endif
@ -130,7 +131,6 @@ isl38xx_trigger_device(int asleep, void __iomem *device_base)
current_time.tv_sec, (long)current_time.tv_usec,
readl(device_base + ISL38XX_CTRL_STAT_REG));
#endif
udelay(ISL38XX_WRITEIO_DELAY);
reg = readl(device_base + ISL38XX_INT_IDENT_REG);
if (reg == 0xabadface) {
@ -144,7 +144,9 @@ isl38xx_trigger_device(int asleep, void __iomem *device_base)
while (reg = readl(device_base + ISL38XX_CTRL_STAT_REG),
(reg & ISL38XX_CTRL_STAT_SLEEPMODE) == 0) {
udelay(ISL38XX_WRITEIO_DELAY);
#if VERBOSE > SHOW_ERROR_MESSAGES
counter++;
#endif
}
#if VERBOSE > SHOW_ERROR_MESSAGES
@ -152,10 +154,6 @@ isl38xx_trigger_device(int asleep, void __iomem *device_base)
"%08li.%08li Device register read %08x\n",
current_time.tv_sec, (long)current_time.tv_usec,
readl(device_base + ISL38XX_CTRL_STAT_REG));
#endif
udelay(ISL38XX_WRITEIO_DELAY);
#if VERBOSE > SHOW_ERROR_MESSAGES
do_gettimeofday(&current_time);
DEBUG(SHOW_TRACING,
"%08li.%08li Device asleep counter %i\n",
@ -170,7 +168,6 @@ isl38xx_trigger_device(int asleep, void __iomem *device_base)
/* perform another read on the Device Status Register */
reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
udelay(ISL38XX_WRITEIO_DELAY);
#if VERBOSE > SHOW_ERROR_MESSAGES
do_gettimeofday(&current_time);
@ -186,7 +183,6 @@ isl38xx_trigger_device(int asleep, void __iomem *device_base)
isl38xx_w32_flush(device_base, ISL38XX_DEV_INT_UPDATE,
ISL38XX_DEV_INT_REG);
udelay(ISL38XX_WRITEIO_DELAY);
}
}

10
drivers/net/wireless/prism54/islpci_eth.c
View file

@ -226,17 +226,17 @@ islpci_eth_transmit(struct sk_buff *skb, struct net_device *ndev)
priv->data_low_tx_full = 1;
}
/* set the transmission time */
ndev->trans_start = jiffies;
priv->statistics.tx_packets++;
priv->statistics.tx_bytes += skb->len;
/* trigger the device */
islpci_trigger(priv);
/* unlock the driver code */
spin_unlock_irqrestore(&priv->slock, flags);
/* set the transmission time */
ndev->trans_start = jiffies;
priv->statistics.tx_packets++;
priv->statistics.tx_bytes += skb->len;
return 0;
drop_free:

3
drivers/net/wireless/wavelan_cs.c
View file

@ -4608,9 +4608,8 @@ wavelan_attach(void)
#endif
/* Initialize the dev_link_t structure */
link = kmalloc(sizeof(struct dev_link_t), GFP_KERNEL);
link = kzalloc(sizeof(struct dev_link_t), GFP_KERNEL);
if (!link) return NULL;
memset(link, 0, sizeof(struct dev_link_t));
/* The io structure describes IO port mapping */
link->io.NumPorts1 = 8;

3
drivers/net/wireless/wl3501_cs.c
View file

@ -1965,10 +1965,9 @@ static dev_link_t *wl3501_attach(void)
int ret;
/* Initialize the dev_link_t structure */
link = kmalloc(sizeof(*link), GFP_KERNEL);
link = kzalloc(sizeof(*link), GFP_KERNEL);
if (!link)
goto out;
memset(link, 0, sizeof(struct dev_link_t));
/* The io structure describes IO port mapping */
link->io.NumPorts1 = 16;