From a7cdb778e4d39154775e6cf8e405014aa25fac16 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 20 May 2022 12:21:35 +0530 Subject: [PATCH] clk: qcom: gpucc: Update the frequency for GPU core clock for blair Add support for 700MHz for GPUCC core clock. Change-Id: Ieb1e5514df0c00f3c6d0eb3cf8d9baccd214ba07 Signed-off-by: Taniya Das --- drivers/clk/qcom/gpucc-blair.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/gpucc-blair.c b/drivers/clk/qcom/gpucc-blair.c index 51ce96715ca7..8749c0c5fefd 100644 --- a/drivers/clk/qcom/gpucc-blair.c +++ b/drivers/clk/qcom/gpucc-blair.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -200,6 +201,7 @@ static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { F(390000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), F(490000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(700000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), F(770000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), F(840000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), F(900000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),