From a8d6cbc9bb4d65dd1fac9fd8acc4d5157b21fca1 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Thu, 25 Mar 2021 20:12:03 +0530 Subject: [PATCH] ARM: dts: msm: Add ACD control register values for Yupik GPU Add the dvm values to enable ACD support for all GPU power levels. Change-Id: Ia840a8c22fc86f62b9ed105e4aecb1fbd175eff2 --- qcom/yupik-gpu.dtsi | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi index c09538cf0ddc..02ca156dc51f 100644 --- a/qcom/yupik-gpu.dtsi +++ b/qcom/yupik-gpu.dtsi @@ -171,7 +171,7 @@ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <802000000>; + qcom,gpu-freq = <812000000>; qcom,level = ; qcom,bus-freq-ddr7 = <11>; @@ -181,6 +181,8 @@ qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@1 { @@ -195,6 +197,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@2 { @@ -209,6 +213,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@3 { @@ -223,6 +229,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@4 { @@ -237,6 +245,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@5 { @@ -251,6 +261,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; }; }; @@ -264,7 +276,7 @@ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <802000000>; + qcom,gpu-freq = <812000000>; qcom,level = ; qcom,bus-freq-ddr7 = <11>; @@ -274,6 +286,8 @@ qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@1 { @@ -288,6 +302,8 @@ qcom,bus-freq-ddr8 = <9>; qcom,bus-min-ddr8 = <8>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@2 { @@ -302,6 +318,8 @@ qcom,bus-freq-ddr8 = <8>; qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <10>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@3 { @@ -316,6 +334,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@4 { @@ -330,6 +350,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@5 { @@ -344,6 +366,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; }; }; @@ -366,6 +390,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@1 { @@ -380,6 +406,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@2 { @@ -394,6 +422,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; }; }; qcom,gpu-pwrlevels-3 { @@ -415,6 +445,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <6>; qcom,bus-max-ddr8 = <8>; + + qcom,acd-level = <0x802B5FFD>; }; qcom,gpu-pwrlevel@1 { @@ -429,6 +461,8 @@ qcom,bus-freq-ddr8 = <3>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882F5FFD>; }; }; };